Hello everybody,
I have designed a schematic in OrCAD Capture CIS and
then created netlist. And then I am able to open the file in OrCAD
Layout Plus. But on selecting Autoroute Spectra-->Launch Spectra, I
get the series of messages
1.) Too many parameters were specified on command line.
2.) Layout to SPECCTRA Version 16.0.0
Copyright 1985-2006 Cadence Design Systems, Inc.
ERROR (Layout to SPECCTRA), Unexpected DB Version found
Translate time 0 seconds
3.) The problem preventing translation of your file into DSN format must be corrected before the SPECTRA router can be used.
Please help me solve this issue.
Thanks in advance.
Regards,
Anay
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Autoroute problem
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ultra pcell with dbCreateParamInstByMasterName
Hi All,
I am creating a ultra pcell consists of pch_fet cell (pcell) using dbCreateParamInstByMasterName. The pcell has "l" and "w" parameters. While Instantiating the ultra pcell with required l and w, it looks only l and w are changing. But, other parameters like dummies w and l are not changing. It seems the callbacks associated with l and w of pch_fet are not executed.
Can somebody tell me how to overcome this issue. How to get the callbacks associated l and w of basic pcell.
Thanks,
bsrin
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pnoise and pac contradiction
Hi,
First I want to know hoe does spectre compute flicker and thermal noise
1) using a current modelbetween drain and source
2) using a voltage model at the gate
I am using BSIM 4.5 models where doc says both are modled as current source.
Second,
I have simulated noise transfer function of thermal & flicker noise
of M1 from RF to IF using pss+pnoise and noise separation.
(sideband=+1). Why are they different? I believe both thermal and
flicker are modeled as current source and hence transfer function should
be same. The transistor model is BSIM 4.5 and noise model is holistic.
Is it because contribution from noise source modulation is different for
them?
I tried modeling the noise using a current source (red)
and use PXF analysis. But the gain is around 150 in contrast with 1.2K
from pnoise simulation. Why is pxf resulting in such low value? Is this
method of modeling noise not correct?
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Regarding more DRCs at routing for 28nm designs using routeDesign command using encan advanced license
Hi,
Iam working on 28nm design using soc encounter with the following steps,
Placement -> prectsopt -> CTS -> postcts_opt for setup and hold -. routing -> postroute opt
1)Iam using padding for the flops at placement stage.
2) CTS done by using the CellHalo for clock buffers,
3) Routing is done using routeDesign command
Here, at routing stage Iam getting lot of DRCs around #6000 while routing the design, but when I do verifyGeometry with the default options Iam getting around 1000 DRCs. confusion with this number.
"routeDesign shows different DRC count than VerifyGeometry"
Iam using the following nanorouting settings for routing the design.
setNanoRouteMode -routeWithViaOnlyForStandardCellPin 1:2
setNanoRouteMode -routeWithViaInPin false
setNanoRouteMode -routeUseMultiCutViaEffort medium
setNanoRouteMode -drouteAutoStop false
routeDesign
Please give me suggestions/advises inorder to reduce the number of DRC count at routeDesign.
Is any switch should be added while routing the design with setNanoRoueMode?
FYI Iam using EDI 11.13V tool.
Thank you,
Waiting for response.
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Standard way to report/calculate leftover space on the board?
I don't have much faith in this method personally, but I'm facing the expectation that we report the space occupied by parts relative to the overall size of the board.
It's great that I can query the placement void and get the area in mm2, is there a whole-board report to allow me to avoid bringing Excel into this...
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Minarea violation in SOC encounter
Hi, I want to know what "Minarea violation" is, and how can I solve it?? I have 3 Minarea violations in Geometry verifying by SOCencounter...
thanks alot
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Gate Level Sim - SDF annotation debug
Hi,
I am trying to annotate an SDF to my gate level synthesis netlist and I am seeing some strange behaviour.
When I annotate using just the netlist, cell_lib and sdf , everything works fine. However, when I try to annotate using the testbench and providing the full scope to the netlist within the verification environment (SCOPE=test_env.<scopetodigtop>.udig_top), I see thousands of
SDFNEP, SDFNET errors. The paths and timing checks which ncelab is complaining about definitely do exist in the cell_lib verilog, and the scope is definitely correct. I have tried modifying the scope just to make sure that it was correct and with anything apart from these settings the annotator complains that the scope is incorrect and refuses to proceed.
What am I missing and what is the best way to debug this ?
I have tried versions incisiv/11.10.011, incisiv/12.10.011 and incisiv/12.20.008
thanks
Andy
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Design partition in soc encounter 10.1
I am new to soc encounter, Can anyone guide me how to do the design partition flow. Due to lincese problem It does not read the Power domain (Low power) commands, MSMV and cpf file.
The design TOP has two modules u00 and u01. These two modules has separate external power suply. How to separate these two mdoules in the core?
How to move the module inside the core area after loading the design?
I started with the commands,
createFence u00 7 7 16 45
definePartition -hinst u00 -coreSpacing 1.0 1.0 1.0 1.0 -railWidth 0.0 -minPitchLeft 0 -minPitchRight 0 -minPitchTop 0 -minPitchBottom 0 -reservedLayer { 1 2 3 4 5 6 7 8} -pinLayerTop { 2 4 6 8} -pinLayerLeft { 3 5 7} -pinLayerBottom { 2 4 6 8} -pinLayerRight { 3 5 7} -placementHalo 0.0 0.0 0.0 0.0 -routingHalo 0.0 -routingHaloTopLayer 8 -routingHaloBottomLayer 1
createPtnCut -ptn u00 7 7 12 45
Thank you,
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Add space to the top and bottom of standard cells
Hi all,
In my design, if two cells of a specific cell type are stacked on the top of each other, a lower layer is shorted.
Is there anyway to add space to the top and bottom of kind of cell type?
Thanks,
Nga.
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Design is tight after placing cells
Hello
After placing a design all the cells are concentrated in one place, the tool takes a very long time to finish and after a lot of iterations I have geometry and shorts violations.
I set the Clock to a very low frequency (in ps) hoping to relax the timing constrains in rtl compiler.
Period 5000000
Delay 10000
OutDelay 10000
I also used :
modulePadding -uniformDensity true
The utilization is very low as well (0.4)
Also, during routing I got the following warnings from encounter:
#WARNING (NREX-28) The height of the first routing layer M1 is 0.000000. It should be larger than 0.000000
#WARNING (NREX-29) The metal thickness of routing layer M1 is 0.000000. It should be larger than 0.0. Add this to the technology information for better accuracy.
#WARNING (NREX-30) Please also check the height and metal thickness values for the routing layers heigher than routing layer M1
#WARNING (NREX-4) No Extended Cap Table was imported. Not enough process information was provided either and default Extended Cap Table database will be used.
#WARNING (NRAG-41) The M1 user tracks are removed and regenerated from M3
# M1 H Track-Pitch = 0.200 Line-2-Via Pitch = 0.205
#WARNING (NRAG-44) Track pitch is too small compared with line-2-via pitch
So I have two questions,
- How can I make sure the cells are spread a better in all the available area?
- For the warnings: To fix it, should i set a parameter in the lef file? if so, which one?
Thanks!
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Upon netlist import, SIGNAL_MODEL proberty getting deleted.
Part of the process to create xnets is using the SIGNAL_MODEL property.are created in Allegro. Normally we are able to rename all components, delete the SIGNAL_MODEL property, and back-annotate to Concept. We do not save the brd file where the SIGNAL_MODEL property was deleted. On the schematic side, import physical is done to receive the new ref des. A new netlist is then created and imported back to Allegro to ensure the schematic and brd file are in sync.
In this particular case, importing the new netlist deletes the SIGNAL_MODEL property from the brd file, causing havoc on our xnets and contraints. This is not happening on our other projects. We use the statement "retain_existing_xnets_diffpairs 'ON' " in the cpm file to ensure no constraints are migrated from Concept to Allegro.
Only difference in the cpm files between the problem project and one that works okay are things like project names or revision levels. I have tried:
1. Do a "copy project" of the project that functions okay, then copying the schmatic files from problem project over.
2. Import design, after deleting all schemtic pages from a good project.
3. Re-checking "Packager XL" setup in projmgr.
All the results are the same.
Any suggestions?
Thank you
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ADE XL remains in "pending" state
hello,
i decided to try ADE XL as i wanted to run temp/corner sweeps. i was able to set everything up, but when i start the simulation, it just sits in "pending" state until the sim times-out. has anyone encountered a similar issue, or has suggestions i can try?
thanks in advance for the help.
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change the line font of a rectangle?
Hi all,
I am trying to create a rectangle, using axlDBCreateRetangle, but there does not seem to be an option for line font. I want to use PHANTOM. Is there a way to change the line font in skill? I know I can change a "line" with axlChangeLineFont, but a rectangle is considered a shape in allegro.
Anyone have a work around for this?
Thanks,
Jerry
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How do I properly format a imported properties file into SKILL to create shapes
I wrote a simple SKILL script which pulls the properties off a shape and prints into a text file.
LayerPair: ("m1" "drawing")
ShapePts: ((0.0 0.0) (100.0 100.0))
PropertyName: Name PropertyValue: "p3"
LxLyCoor: 0.000000:0.000000
DxDy: 100.000000:100.000000
EndShape!
I may want to add minor modifications to the coordinates then read the file back into SKILL and re-create the shapes using dbCreateRect, dbCreatePolygon..feeding it the same info I pulled off the shape.
I use an 'infile and gets' to read each line. The lines come in with the following syntax.
"LayerPair: (\"m2\" \"drawing\") \n"
I've tried parseString and other manipulations unsuccessfully. I'm sure there is a clever and obvious way to do this.
I did look at the online support, forum and google but I may not be phrasing the question correctly.
I'd appreciate some pointers on what I'm doing wrong with the syntax..this should be simple with SKILL.
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axlDBCreateShape attach to via?
Hi
I've used axlDBCreateShape and attached it to a symbol with succes in the past.
Now I would like to be able to do the same for a via but seems like this is not possible or is there a way to do this?
Best regards
Ole
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ViVA setting to remember waveform setup
What is the procedure to set the ViVA so that everytime after simulation is done, the previous waveform display format, such as signal order, signal groups,... is the same as before?
By default it uses the default, that is all signals are crowded togrther. I have to re-group it...
It is kind of annoying to do this after each simulation if there are many signals to watch.
In ADE I selected all the items in "What to Save" section in saving state form. I see there is Waverform Setup, but it seems not what I want.
can anybody help?
Thanks
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ultra pcell with dbCreateParamInstByMasterName
Hi All,
I am creating a ultra pcell consists of pch_fet cell (pcell) using dbCreateParamInstByMasterName. The pcell has "l" and "w" parameters. While Instantiating the ultra pcell with required l and w, it looks only l and w are changing. But, other parameters like dummies w and l are not changing. It seems the callbacks associated with l and w of pch_fet are not executed.
Can somebody tell me how to overcome this issue. How to get the callbacks associated l and w of basic pcell.
Thanks,
bsrin
↧
↧
How to deposit simulation result into a file?
Hi, I am wondering is there a way to save an output into a file, like a .txt which it is easy to read from.
Specifically, in the "Setting outputs" of Virtuoso Analog Design Environment (ADE) I have:
Name: PhaseMargin
Expression: (phaseMargin((VF("/Vout") / (VF("/Vin+") - VF("/Vin-")))) + 180)
After simulation, I got 80 degree displayed.
But is there a way to save this '80' into a .txt file?
I am using SpectreS as the simulator. I think there are some commands to output results.
Any answer is appreciated.
Thanks,
Alex
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simulation run time
Hi,
I have a ocean script that I saved from ADE. How can I record the time it takes for the simultion to run so that I can write it to a file?
Thanks,
Milind
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bindkey definitions issues
Got a little problem here. I have a massive set of custom bindkeys defined - these have worked fine for years (with a little process dependant tweaking)...
Recently started a new process - and moved to version Cadence ICADV12.2-64b.400.1
Now my shift and also control F keys no longer load the associated procedures I have defined in my key.il file.
These issues are specific to the function keys
the regular key (no shift or ctrl combo) works fine
Shift+ the_function key (ex. shift+F1) does not run the assigned function... instead duplicates the actions of the regular function key.
Ctrl + the function key combos does not work at all... this is true for F1 thu F12
for example:
In my key file I have the following code...
alias bk hiSetBindKey
LAY = "Layout"
SCH = "Schematics"
bk(LAY "<Key>F3" "leHiMarkNet()")
bk(LAY "Shift<Key>F3" "leHiUnmarkNetAll()")
bk(LAY "Ctrl<Key>F3" "listInstancesInViewingArea()")
F3 works fine and performs leHiMarkNet command
shift F3 does not unmark the net... instead it performs the leHiMarkNet command
ctrl + F3 does not do anything...Nada.
so...question...is this an issue with teh new cadence version?
Note: To eliminate the possibility that my key file is getting stomped on by the group loads... I have tried to direct load the key assignment via the CIW command line...it looks like it loads fine (no error messages and returns "t"... but then it still performs incorrectly as described above.
Suggestions????? any help would be greatly appreciated... since a vast majority of our team uses my custom setup.
Thanks,
Terry
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