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removing duplicate items on a list

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Hi everyone,

Is their a function that that removes duplicates in a certain list?.

example:

input list is..

listWithDuplicate = ( "a" "b" "c" "d" "a" "c" "d" "a" "a")

after running the certain function, the output should look like this..

newList =  ( "a" "b" "c" "d")..

I am thinking of using looping statements but using loops will affect the time to run the program specially when the list consist of many items..

Thanks in Advance..


Strange error putprop

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 Hi,

       I am  running a script (pasted below) in Ocean. The simulations have already finished fine. This script just selects the run and extracts measurements from it. It runs fine for a few iterations then it gives me this error (on the 12th iteration)

 *Error* putprop: first arg must be either symbol, list, defstruct or user type - nil

 This happens right after the plot command of IBIAS_FIN since I see this on the terminal:

*Warning* Wave82 is not a waveform object that can be displayed and
          will be DELETED automatically.
          name: "IBIAS_FIN"

 But if I restart the script onwards from the 12th iteration, the12th iteration works fine it shows the same problem on the 13th iteration. If I execute the script commands 1 at a time for the 12th iteration they work fine.

   Please help me figure out why I am getting this error. These measurement statements are from the ocean script generated by ADE, I did not change them so I don't know why they cause a problem.

 

Thanks,

Milind

 

 

OCEAN SCRIPT:

 

for(i 1 54
    sprintf(corDir "%s%d/psf" "/home/milind/BIAS_TB_TRAN/corner" i)
    openResults(corDir )
    IBIAS_TEMP = IS("/I0/M38/D")
    plot( IBIAS_TEMP ?expr '( "IBIAS_TEMP" ) )
    IBIAS_FIN = value(IS("/I0/M38/D") VAR("gt"))
    plot( IBIAS_FIN ?expr '( "IBIAS_FIN" ) )
    IBIAS_AT_POK = value(IT("/I0/M38/D") cross(VT("/POK") (VAR("vsup") / 2) 1 "rising" nil nil))
    plot( IBIAS_AT_POK ?expr '( "IBIAS_AT_POK" ) )
    POK_Time = cross(VT("/POK") (VAR("vsup") / 2) 1 "rising" nil nil)
    plot( POK_Time ?expr '( "POK_Time" ) )
    IBIAS_DC = IDC("/I0/M38/D")
    plot( IBIAS_DC ?expr '( "IBIAS_DC" ) )
    ISUP_DC = IDC("/V0/MINUS")
    plot( ISUP_DC ?expr '( "ISUP_DC" ) )
    ISUP_FIN = value(IT("/V0/MINUS") VAR("gt"))
    plot( ISUP_FIN ?expr '( "ISUP_FIN" ) )
    IBIAS_AFGL = value(IS("/I0/M38/D") (2 * VAR("gt")))
    plot( IBIAS_AFGL ?expr '( "IBIAS_AFGL" ) )
    ISUP_AFGL = value(IT("/V0/MINUS") (2 * VAR("gt")))
    plot( ISUP_AFGL ?expr '( "ISUP_AFGL" ) )
    POK = VT("/POK")
    plot( POK ?expr '( "POK" ) )
    VSUP = VT("/VDD")
    plot( VSUP ?expr '( "VSUP" ) )
    IBIAS = IT("/I0/M38/D")
    plot( IBIAS ?expr '( "IBIAS" ) )
    LG_Phase = phaseDegUnwrapped(getData("loopGain" ?result "stb"))
    plot( LG_Phase ?expr '( "LG_Phase" ) )
    LG_dB20 = db(mag(getData("loopGain" ?result "stb")))
    plot( LG_dB20 ?expr '( "LG_dB20" ) )
    Phase_Margin = value(getData("phaseMargin" ?result "tran_stb_margin-tran_margin.stb") 0.01)
    plot( Phase_Margin ?expr '( "Phase_Margin" ) )
    PM_Freq = value(getData("phaseMarginFreq" ?result "tran_stb_margin-tran_margin.stb") 0.01)
    plot( PM_Freq ?expr '( "PM_Freq" ) )
    Gain_Margin = value(getData("gainMargin" ?result "tran_stb_margin-tran_margin.stb") 0.01)
    plot( Gain_Margin ?expr '( "Gain_Margin" ) )
    GM_Freq = value(getData("gainMarginFreq" ?result "tran_stb_margin-tran_margin.stb") 0.01)
    plot( GM_Freq ?expr '( "GM_Freq" ) )
    LG_DC = value(value(dB20(getData("loopGain" ?result "tran_stb-tran_stb")) 1e-05) "time" 0.01)
    plot( LG_DC ?expr '( "LG_DC" ) )
   
    if(i==1 then
        fileHandle = outfile("/home/milind/BIAS_TB_TRAN/data.csv" "w")
        ocnPrint( ?output fileHandle ?numberNotation 'engineering  "vdd=5" "ttttttt" "-40" Phase_Margin PM_Freq )
        close(fileHandle)
    else
        fileHandle = outfile("/home/milind/BIAS_TB_TRAN/data.csv" "a")
        ocnPrint( ?output fileHandle ?numberNotation 'engineering  "vdd=5" "ttttttt" "-40" Phase_Margin PM_Freq )
        close(fileHandle)   
    )
)

Regarding LibGen

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 Hi All ,

Can any one clarify my doubts regarding LibGen which will generate the cell libraries which are required for the power grid analysis.

 

1.I have seen five steps in LibGen , XTC , QX , Model Tables , Thunder and Power Grid Views Generation  , what happens in each of these steps and what are the required input files for these steps and what are the output reports of these steps?.

 

2.I read like LibGen is independent of Design but i have seen in the diagram of LibGen like one of the input for LibGen is GDS-II , why GDS-II is required for LibGen?

 3. what is the Exact output of the LibGen step?

4.what is the difference between power grid views and power grid view library?

5.what does the main function of  thunde?

6.what is the function of Power Meter?

7.how does vstorm calulates the voltage drop by taking the thunder and power meter outputs as inputs for vstorm.

8.what is the impact of electro migration on IR-Drop?

 

Can any one clarify my doubts.

-Thanks

 

allegro:can not select unplaced component

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I have a PCB file(.brd) and Schematic(.pdf) from our supplier. Now,I draw the Schematic in Orcad,the footprint of the part is from PCB file. Now,something happend. what i did is as follows.

1. I export the package from pcb file.

2. Draw the Schematic in Orcad.the footprint of the part is from pcb file

3.Create netlist in Orcad.

4. open the pcb file(.brd) in allegro pcb editor

5. inport the netlist.

 Now,after inporting the netlist of the Schematic, I find all components can not be placed. I want to know what is the reason, How I solve it. Thank you

                                                                   

IPC-7351 Level C

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Hi all,

Has anyone experienced on using of IPC-7351 level C footprints? Presently I'm using it in one of our project which is a very dense and space constraint board. My concern is,

  1. Is there anything issues we have to take a special care, as to avoid any DFA/DFM?
  2. What is the minimum space we have to keep for two level C footprints (major's and passive's) to avoid any assembly and manufacturing issues?

Any input will be appreciated.

Thanks,

Shiva.

sensitivity analysis on SP simulation?

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 Hello,

 

Has anyone  investigated to extend the spectre sensitivity analysis ( ac, dc) on sp simulation at a fixed frequency?

 

Regards

Power and delay calculation in Virtuoso

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Sir,

I have drawn the schematic of my Cmos full adder design in Virtuoso and I got the output voltage waveforms. I dont know how to calculate the Power and delay for my design. Please help me to get the result for my design.

Thanks,

Citharthan D

Mobile-91-8939498903 

Pcell symbol creation using SKILL

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Hi,

 

I'm using SKILL code as below to generate a Pcell symbol (i.e. number of symbol terminals depend on CDF parameter).

However, every time when I load these code in CIW (i.e. IC615) into a library which attached to cdsDefaultTechLib, it will complain below warnings:

 *WARNING* (DB-270000): dbiSetCellViewDBUPerUU: The DBUPerUU attribute for viewType 'schematicSymbol' cannot be set to 1000 because it would introduce conflicts in the specified tech graph

 *WARNING* (DB-270000): dbSetCellViewUserUnitName: The UserUnits attribute for viewType 'schematicSymbol' cannot be set to 'micron' because it would introduce conflicts in the specified tech graph

 

The generated symbol seems to have incorrect size and scaling. Anyone knows how to workaround this?

 

=================================================================================

 pcDefinePCell(
    ; target cellView
    list(ddGetObj("test") "myparsubckt" "symbol" "schematicSymbol")

    ; formal parameters
    (
    (padNum 1)
    )

    let((dY justify1 labelId netId
        rectId s
        xEnd xLabel2 xLoc yLoc sc
        h xShape yShape
    )
    pcCellView~>DBUPerUU=1000.0
    pcCellView~>userUnits="micron"
    sc = 0.16
    h = padNum
    dY = (h - 1) * 0.125
    xLoc = 0.625
    ;----------------------------------------------------------------
    ; Create outline
    ;----------------------------------------------------------------
    dbCreateRect(pcCellView
        '("device" "drawing")
        list(0.125 * sc:-0.135 * sc
        0.5 * sc:(0.17 + dY) * sc
        )
    )
    dbCreateRect(pcCellView
        '("instance" "drawing")
        list(0 * sc:-0.25 * sc
        xLoc * sc:(0.17 + dY) * sc
        )
    )
    ;----------------------------------------------------------------
    ; Labels
    ;----------------------------------------------------------------
    sprintf(s "Parasitic Network")
    dbCreateLabel(pcCellView
        '("pin" "label")
        0.3125 * sc:(0.12 + dY) * sc s "centerCenter"
        "R0" "stick"
        0.05 * sc
    )
    labelId = dbCreateLabel(pcCellView
        '("annotate" "drawing7")
        xLoc * sc:(0.2275 + dY) * sc "cdsName()" "upperRight"
        "R0" "stick"
        0.05 * sc
        )
    labelId~>labelType="ILLabel"
    ;----------------------------------------------------------------
    ; Pins
    ;----------------------------------------------------------------
    for(i 1 padNum
        yLoc = (h - i) * 0.125
        xLoc = 0
        xEnd = 0.155
        justify1 = "lowerRight"
        xLabel2 = 0.15625
        xShape = 0.15625
        yShape = ((h - i) * 0.125)
        dbCreateRect(pcCellView
        '("device" "drawing")
        list(xShape * sc:(yShape - 0.05) * sc
            (xShape + 0.1) * sc:(yShape + 0.05) * sc
        )
        )
        dbCreateLine(pcCellView
        '("device" "drawing")
        list(xLoc * sc:yLoc * sc
            xEnd * sc:yLoc * sc
        )
        )
        rectId = dbCreateRect(pcCellView
            '("pin" "drawing")
            list((xLoc - 0.025) * sc:(yLoc - 0.025) * sc
            (xLoc + 0.025) * sc:(yLoc + 0.025) * sc
            )
        )
        sprintf(s "p%d" i)
        netId = dbCreateNet(pcCellView s)
        dbCreateTerm(netId s "inputOutput")
        dbCreatePin(netId rectId)
        sprintf(s "cdsTerm(p%d)" i)
        labelId = dbCreateLabel(pcCellView
            '("annotate" "drawing8")
            xLoc * sc:(yLoc + 0.0625) * sc s justify1
            "R0" "stick"
            0.05 * sc
        )
        labelId~>labelType="ILLabel"
    )
    for(i 1 padNum
        yLoc = (h - i) * 0.125
        xLoc = 0.625
        xEnd = 0.5
        justify1 = "centerLeft"
        xLabel2 = 0.29
        sprintf(s "b%d" i)
        dbCreateLabel(pcCellView
        '("pin" "drawing")
        xLabel2 * sc:yLoc * sc s justify1
        "R0" "stick"
        0.05 * sc
        )
    )
    t
    )
)

 =================================================================================

 


PAL simulation

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I need to simulate a PAL10H8 (included in DIG_PAL.OLB library. Parts in PLD.OLBlibrary can not be simulated), but I have got this error:

"ERROR -- Subcircuit PAL10H8 used by X_U1 is undefined"

How can I simulate with that part? Its implementation type is 'PSpice model', and I have a correct JED file... This is part of the .out file:

X_U1         B3 B0 B1 B2 ...

+  ... $G_DPWR $G_DGND PAL10H8 PARAMS: 

+ IO_LEVEL=0 MNTYMXDLY=0 TEXT: JEDEC_FILE="bcd7seg.jed" 

What is the problem? Any idea?

 Thanks in advance 

Orcad 9.0

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I would like to install Orcad 9.0 Capture and Layout on a Windows 8 64-bit laptop. What do I need to do to run the installation?

Help with the circuit rectification

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The circuit is a wireless power transfer for bio micro systems which is implemented with the help of class E amplifier technique, i do facing the trouble of choosing the tranformer, i dont know which kind of transformer to be chosen, i had chosen the XFRM_LINEAR but it does not contain the distance of separation between coils which is important for my work, and also in the receiver section i am facing a serious trouble with the rectification of voltage across the capacitor, i had used the PDIODE/EVALP for building a full wave rectifier but its not giving a proper output, am still having the negative voltage present in the output at the resistor of 300ohms and also the voltage at the capacitor is also getting limited, without the usage of the rectification i am getting a peak-peak voltage of +/- 10.4V at resistor, but the result i need to get is 5V DC voltage after the rectification of the output and it has to charge a capacitor, after many trials i made, i was not able to get it.

please be of help

Have to add all Libraries each time.

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I generally add all the available Library all the time so it is easy search parts amoung them. When I was using OrCAD Capture Version 16.0, when I once add all the libraries, Capture use to remember and show it that way whenever I start the Capture, but now in OrCAD capture version 16.5 SPB it looses that information (libraries that are added in the workspace) everytime I restart the Capture. Is there some setting somewhere that I can enable that'll allow it to remember that. Could anyone help?

help with the 5V voltage regulators

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i was having an output voltage of 11V on a circuit, but i need a voltage regulator that can make it to the 5V steady DC voltage, i dont know what library in pspice edition 16.5 has this function, please help me

NC Drill Problem

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I've recently completed a design on a new PCB and I've done two things I haven't done so far with PCB Designer.  The first was to mount a component at an odd angle (13 degrees).  This worked well.  This component also has two non plated slots for alignment pins on the component.  I created the non-plated slots using Pad Designer and incorporated the slots into my package symbol as a mechanical element.  Here's where I'm running into a problem -

 I can see the slots on the board when looking at it in PCB Designer 16.5.  I can toggle the holes on and off on the screen, and the slots even show up on the 3D view of the PCB.  The slots and their respective symbol show up on the Drill Legend and they are included in the hole count, but, when I generate the NC Drill file, the slots aren't showing up.  I missed it at first, but the PCB fabricator sent me an email and wanted to know what to do with the oval-shaped spots in the solder mask, because there was no NC Drill data for that area.  Sure enough, I opened up the drill data using Pentalogix Viewmate, and the slots are not there.   The board fab place is going to manually put the slots in for my prototypes, so I'm OK for right now, but for production boards, I'm going to need this data to be present.

 I'm probably missing some setting in the drill parameters or something, but I have no idea what it is.  Has anybody else run into this?  Does anybody have any idea what I'm doing wrong?  I've tried changing a few settings in the NC Parameters, but so far, nothing I've tried has worked.

Off Grid (Misaligned) components and circuits in Capture.

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I've imported a project made by OrCAD Capture 16.0 into OrCAD Capture 16.5 SPB, and all the components and wires have become misalligned to the grid. Thus it doesn't allow me to connect new components to the same. 

In my search here I found this link in this forum: http://www.cadence.com/Community/forums/p/11756/15426.aspx#15426

which mentions similar issue but the solution given needs lots of rework for me as different group of circuits are misaligned by different distance.  

Is there a way to solve this in a more simpler way?


ADE XL and ocean scripts

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Hi,

I'm trying to run simple ocean scripts from ADE XL in cadence IC 615. To begin with I only run a simple transient simulation. I specify the test under Tests in the data view and load a saved state from ADE L. Then running the simulation by using the run button works as it should. However, when I simply save the ocean script from ADE XL and then load it I get some problems.

First, if the ADE XL window is open and the ocean script is loaded I get the following info and error:

 

INFO (ADEXL-1642): The cell view "Library: test Cell: Invx4TB View: adexl2" is already open. It will not be opened in a new window

*Error* There is no OCEAN XL session. Use ocnxlTargetCellView()

command to create a session.

 

If I look in the ocean script then I can see that the command ocnxlTargetCellView() was already generated when I saved the script from ADE XL so I don't understand why it is displaying this error message. 

 

When I close the ADE XL window and run the script, i get problems with the model file i.e. the models for the transistors are undefined.

 

Does anybody know if I'm doing something wrong or missing somehting or if it's another error? I'm a new beginner when it comes to ADE XL.

 

Thanks.

Rotating parts

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I have a group of parts selected, I want to rotate the group but when I selecte rotate, they rotate around their own individual axis.

How can I get them to rotate as a group and not individaully?

Tom

How to create a quick report menu in allegro symbol edit.

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How to create a quick report menu in allegro symbol edit.

regarding transition time?

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how we can know transition time using spef?

Encounter terminated by internal (SEGV) error/signal...

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Hi,

I was trying to click Ruler(K) Button on the encounter screen , Encounter dies with the message "Encounter terminated by internal (SEGV) error/signal...".  is there any suggestion to solve it ?  thanks

My encounter version:8.1    system is CentOS 6.2, 64 bit

the log file is below:

 @(#)CDS: First Encounter v08.10-p004_1 (32bit) 11/04/2008 14:34 (Linux 2.6)
@(#)CDS: NanoRoute v08.10-p008 NR081027-0018/USR58-UB (database version 2.30, 67.1.1) {superthreading v1.11}
@(#)CDS: CeltIC v08.10-p002_1 (32bit) 10/23/2008 22:04:14 (Linux 2.6.9-67.0.10.ELsmp)
@(#)CDS: CTE v08.10-p016_1 (32bit) Oct 26 2008 15:11:51 (Linux 2.6.9-67.0.10.ELsmp)
@(#)CDS: CPE v08.10-p009
--- Starting "First Encounter v08.10-p004_1" on Fri Dec 28 09:40:24 2012 (mem=62.2M) ---
--- Running on localhost (x86_64 w/Linux 2.6.32-220.el6.x86_64) ---
This version was compiled on Tue Nov 4 14:34:21 PST 2008.
Set DBUPerIGU to 1000.
Set Default Mode Total Cap Scale Factor to 1.00
Set Detail Mode Total Cap Scale Factor to 1.00
Set Coupling Total Cap Scale Factor to 1.00
Set Total Res Scale Factor to 1.00
Set net toggle Scale Factor to 1.00
Set Shrink Factor to 1.00000
<CMD_INTERNAL> uiSetTool ruler
Encounter terminated by internal (SEGV) error/signal...
*** Stack trace:
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(syStackTrace+0x146)[0xd1c3d2f]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter[0x8bc653e]
[0xf77aa410]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z14winTextExtentsP7winsWinP9winsLayerPcPiS4_S4_+0x75)[0xc571c0d]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z12winDrawRulerP7winsWinP9winsRulerP9winsLayeri+0x408)[0xc5b23c0]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z21winEventDrawEditRulerP7winsWinP14winsEventQueue+0x47)[0xc5b2af5]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z15winEventDrawRubP7winsWin+0x50)[0xc5abba4]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z10winDisplayP7winsWin+0x1c2)[0xc57091c]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter[0xc57323a]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(TclServiceIdle+0x59)[0xe0e74f9]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(Tcl_DoOneEvent+0x16e)[0xe0d7e8e]
/home/cad/layout/encounter/encounter/tools/lib/libtq.so(_ZN17TqEventDispatcher13processEventsE6QFlagsIN10QEventLoop17ProcessEventsFlagEE+0xb6)[0xf633007a]
/home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4(_ZN10QEventLoop13processEventsE6QFlagsINS_17ProcessEventsFlagEE+0x31)[0xf670b981]
/home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4(_ZN10QEventLoop4execE6QFlagsINS_17ProcessEventsFlagEE+0x7a)[0xf670ba8a]
/home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4(_ZN16QCoreApplication4execEv+0xa6)[0xf670e016]
/home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtGui.so.4(_ZN12QApplication4execEv+0x27)[0xf6929587]
/home/cad/layout/encounter/encounter/tools/lib/libtq.so(_ZN13TqApplication4execEv+0x320)[0xf6332568]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_Z7fe_mainiPPc+0x33c)[0x8ba95f0]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(main+0x79)[0x8ba96b7]
/lib/libc.so.6(__libc_start_main+0xe6)[0x8b1ce6]
/home/cad/layout/encounter/encounter/tools/fe/bin/32bit/encounter(_ZN7QDialog13keyPressEventEP9QKeyEvent+0x2b5)[0x8ba8cc1]
========================================
               pstack
========================================
Thread 4 (Thread 0xf49e4b70 (LWP 11694)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0xf7777c26 in nanosleep () from /lib/libpthread.so.0
#2  0x093790de in rdaiLicRecheck(void*) ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6
Thread 3 (Thread 0xf3fe3b70 (LWP 11695)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0x009704f1 in select () from /lib/libc.so.6
#2  0x0e0fa66c in NotifierThreadProc ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6
Thread 2 (Thread 0xf35e2b70 (LWP 11696)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0xf7778590 in sigwait () from /lib/libpthread.so.0
#2  0x08bc69b7 in ctrlCHandle(void*) ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6
Thread 1 (Thread 0xf61da700 (LWP 11647)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0x00937d3b in waitpid () from /lib/libc.so.6
#2  0x008d4293 in do_system () from /lib/libc.so.6
#3  0x008d4622 in system () from /lib/libc.so.6
#4  0xf77787ad in system () from /lib/libpthread.so.0
#5  0x0d1c3d96 in syStackTrace ()
#6  0x08bc653e in rdaiErrorHandler(int, siginfo*, void*) ()
#7  <signal handler called>
#8  0x0058f751 in XTextExtents () from /usr/lib/libX11.so.6
#9  0x0c571c0d in winTextExtents(winsWin*, winsLayer*, char*, int*, int*, int*) ()
#10 0x0c5b23c0 in winDrawRuler(winsWin*, winsRuler*, winsLayer*, int) ()
#11 0x0c5b2af5 in winEventDrawEditRuler(winsWin*, winsEventQueue*) ()
#12 0x0c5abba4 in winEventDrawRub(winsWin*) ()
#13 0x0c57091c in winDisplay(winsWin*) ()
#14 0x0c57323a in winiTkDisplay(void*) ()
#15 0x0e0e74f9 in TclServiceIdle ()
#16 0x0e0d7e8e in Tcl_DoOneEvent ()
#17 0xf633007a in TqEventDispatcher::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/lib/libtq.so
#18 0xf670b981 in QEventLoop::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#19 0xf670ba8a in QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#20 0xf670e016 in QCoreApplication::exec() () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#21 0xf6929587 in QApplication::exec() () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtGui.so.4
#22 0xf6332568 in TqApplication::exec() () from /home/cad/layout/encounter/encounter/tools/lib/libtq.so
#23 0x08ba95f0 in fe_main(int, char**) ()
#24 0x08ba96b7 in main ()
========================================
                gdb
========================================
Using: gdb
[Thread debugging using libthread_db enabled]
[New Thread 0xf35e2b70 (LWP 11696)]
[New Thread 0xf3fe3b70 (LWP 11695)]
[New Thread 0xf49e4b70 (LWP 11694)]
0xf77aa430 in __kernel_vsyscall ()

Thread 4 (Thread 0xf49e4b70 (LWP 11694)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0xf7777c26 in nanosleep () from /lib/libpthread.so.0
#2  0x093790de in rdaiLicRecheck(void*) ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6

Thread 3 (Thread 0xf3fe3b70 (LWP 11695)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0x009704f1 in select () from /lib/libc.so.6
#2  0x0e0fa66c in NotifierThreadProc ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6

Thread 2 (Thread 0xf35e2b70 (LWP 11696)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0xf7778590 in sigwait () from /lib/libpthread.so.0
#2  0x08bc69b7 in ctrlCHandle(void*) ()
#3  0xf7770a09 in start_thread () from /lib/libpthread.so.0
#4  0x0097800e in clone () from /lib/libc.so.6

Thread 1 (Thread 0xf61da700 (LWP 11647)):
#0  0xf77aa430 in __kernel_vsyscall ()
#1  0x00937d3b in waitpid () from /lib/libc.so.6
#2  0x008d4293 in do_system () from /lib/libc.so.6
#3  0x008d4622 in system () from /lib/libc.so.6
#4  0xf77787ad in system () from /lib/libpthread.so.0
#5  0x0d1c3d96 in syStackTrace ()
#6  0x08bc653e in rdaiErrorHandler(int, siginfo*, void*) ()
#7  <signal handler called>
#8  0x0058f751 in XTextExtents () from /usr/lib/libX11.so.6
#9  0x0c571c0d in winTextExtents(winsWin*, winsLayer*, char*, int*, int*, int*) ()
#10 0x0c5b23c0 in winDrawRuler(winsWin*, winsRuler*, winsLayer*, int) ()
#11 0x0c5b2af5 in winEventDrawEditRuler(winsWin*, winsEventQueue*) ()
#12 0x0c5abba4 in winEventDrawRub(winsWin*) ()
#13 0x0c57091c in winDisplay(winsWin*) ()
#14 0x0c57323a in winiTkDisplay(void*) ()
#15 0x0e0e74f9 in TclServiceIdle ()
#16 0x0e0d7e8e in Tcl_DoOneEvent ()
#17 0xf633007a in TqEventDispatcher::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/lib/libtq.so
#18 0xf670b981 in QEventLoop::processEvents(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#19 0xf670ba8a in QEventLoop::exec(QFlags<QEventLoop::ProcessEventsFlag>) () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#20 0xf670e016 in QCoreApplication::exec() () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtCore.so.4
#21 0xf6929587 in QApplication::exec() () from /home/cad/layout/encounter/encounter/tools/Qt/32bit/lib/libQtGui.so.4
#22 0xf6332568 in TqApplication::exec() () from /home/cad/layout/encounter/encounter/tools/lib/libtq.so
#23 0x08ba95f0 in fe_main(int, char**) ()
#24 0x08ba96b7 in main ()
A debugging session is active.

    Inferior 1 [process 11647] will be detached.

Quit anyway? (y or n) [answered Y; input not from terminal]

*** INTERRUPTED *** [signal 1]
11647: No such process

 

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