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Custom deep trench capacitor

June 19, 2014, 12:42 am
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Hi,

I am starting out with a project on DRAM memory cells and am using the cadence 45nm tech node. But at this technology, the capacitance from the mimcap and moscaps need a large area. So I was wondering whether there is any way I would be able to add a custom deep trench capacitor to the technology. Please guide me on what I can do at this point to get about 30-50f of capacitance in a small area preferable deep trench since that wouldn't consume so much space on the die. I am thinking of using sentaurus to simulate the capacitance and import the model as spice model into virtuoso. Please tell me whether this can be done. Or is there a simpler way? And could you point me to some application note that uses this or some references about the above?

 

thanks

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Cadence Virtuoso 6.16 model cards

June 19, 2014, 1:23 pm
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Dear All,

I'm using Predictive Technology Model (PTM) model cards on cadence virtuoso 6.16, and drawing the characteristics ( Ids vs Vgs) of nmos and pmos, but I'm getting the characteristics of pmos like nmos (which is wrong), do anyone know what is the reason of that wrong behavior?

Thanks,

Osama

 

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how to add BB Via in internal layer ??

June 9, 2014, 2:45 am
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Hi everyone,

how to add buried via in inner layer even though i assigned the pad stack assigned for following producure. (set up--->assign BB via)

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Power connectivity for SRAMs

June 20, 2014, 7:08 am
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Hello,

Used Encounter successfully on a number of projects but always only with the standard cell library. I want to use some Faraday SRAMs which I've built and integrated into the flow, I'm a little unsure how to connect the power rails up, any help would be appreciated, detail below:   

 

  1.  

    1. Digital core uses M1 and M2 for power rings which are connected to standard cell grid using SRoute

    2. Faraday memory can be built with:

      1. Ringless model

      2. Ring shape model

      3. Port model

    3. Metal layer options for Ringshape model

      1. 2233

      2. 3322

      3. 2244

      4. 4422

      5. 3344

      6. 4433

    4. I’ve built the memories as “Ring shape model” with the power metal option “2233” so the memory power rings are on Metal 2 and Metal 3. SRoute connects the standard cell grid but I’m unsure how to hook-up the power to the memories.

    5. Was I correct in building the memories with rings?

    6. How do you hook up the power, using SRoute?

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Pcell Creation

June 20, 2014, 9:10 am
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Hi All,

I am trying to create a pcell for nmos. I have added a stretchline in X-direction with name length,  saved and compiled to pcell.

While instantiating the pcell in another cell, I am able to see the form asking for length, But cannot see the physical transistor(nmos).

In CIW , I am getting an warning.

WARNING (DB: 270000) :  dbCreateExtParamInst : Invalid String Index.

 

I am using ICADV12.1 version of virtuoso tool.

Can anyone help me.

 

Thanks In Advance.

bsrin

 

 

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How to create a new footprint without using the package symbol wizard?

June 20, 2014, 1:35 am
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Hi. I had created the footprint with the package symbol wizard, but i want to create the footprint manually means i have go to option of package symbol. When i had opened it, i had no idea to what to be do on that. I had insert the pad stack symbols first and then put the outlines of components, then etc etc.... Can anyone provide the clear options what is to be made in the required option. Thanks & Regards, Dhamodharan
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Ultra librarian- .dra file, .psm file

June 8, 2014, 5:48 pm
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Hi all,

 

I am using OrCAD Capture CIS Lite and PCB Editor Lite. I am trying to design a simple circuit. But I'm not able to get the footprint of components. I downloaded the .bxl file from TI website (http://webench.ti.com/cad/cad.cgi) and extract the library using Ultra Librarian.

 I can't find the .dra or .psm files of the component. When I try to create PCB for the circuit, the footprint is missing.

 When I check the property of my components, say MSP430G2xx, the PCB footprint is PW14. But I can't find that file. So that I can place it in the pcb library.

 Can anyone help me out on this issue?

 Thanks! 

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Import Files for Encounter ( Preparing for Encounter)

June 20, 2014, 1:04 pm
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Hello

 

I am using Cadence Virtuoso 6.1.2.

Can you please guide me how to create .v files from a schematic ( lets say of an inverter)?

Also, I wish to create .lef file of my standard cell layout design through Abgen.But I get error ABS 218 amd ABS - 262. I have fixed those errors, still it is a problem. Do you know any other way to get - 

 

1.  .v files ( gate-level netlist - design files) 

2   .lef files   ( layout info )

3.  .lib files ( timing info )

I need these files to start working on encounter. 
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Antenna violations skill code

June 20, 2014, 1:30 pm
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Hi,

   I am trying to figure out the best way to fix antenna vioaltions for custom layout. If anyone have any scripts to help me get started for writing custom skill code to put in antenna diodes for the violations or use a jumper to a high level metal, that would really jump start my effort. 

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Transient Noise Analysis to Calculate PLL Phase Noise

June 20, 2014, 3:04 pm
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 Hi all,

 I was trying to design a charge pump PLL and simulate the phase noise of it. I ran into some convergence problem when I used PSS+PNOISE, therefore I decided to calculate the PLL phase noise with transient nosie analysis discussed in the site below:

http://www.cadence.com/community/blogs/cic/archive/2009/03/26/calculating-large-signal-phase-noise-using-transient-noise-analysis.aspx

Following the setup described in the article, I could obtain the phase noise very close to my calculation. However, the phase noise offset frequency has a very limited range. The article says the phase noise plot will extend from fmin=4/tstop to fmax=fosc/2, where tstop is the transient noise simulation stop time and fosc is the oscillation frequency. In my simulation, fosc=2GHz, and I ran the transisent analysis for 10us, therefore I should get a phase noise plot from 400KHz to 1GHz. However, I only saw the phase noise plot from 2MHz to 1GHz (as shown in the figure). I also tried to increase the transient analysis time, but that didn't help. The other transient setup parameters that I have are

Noise Fmax=20GHz, Noise Fmin=100KHz, Noise Seed=1, Noise Scale=1, Noise Tmin=1ps  and errpreset=moderate

Since I am also interested in the frequency offsets lower than 2MHz, I really want to extend the phase noise plot to the lower frequencies.  I guess the problem is because of my wrong setups of noise Fmax and noise Fmin, but I was actually not quite sure how to set them. Does anyone have any experience on this? Why the phase noise plot from transient noise analysis cannot extend from 4/tstop to fosc/2?

 

Thank you in advance!

 

Faye

 

 

 

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PCELL eval failed, how to debug missing functions?

June 21, 2014, 1:50 pm
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Hello everyone. I'm trying to debug a strange PCELL evaluation error. I had a bunch of layout up and working, but 3 design kit revisions later, I have a bunch of PCELL evaluation errors instead of transistors. I'm sure that this has to do with how my kit is configurued, and I'd like to track it down out of interest. I've tracked down somethings, but I'm not completely familiar with the "internal" gears of Virtuouso. The PCELL error is: 

*WARNING* (DB-270001): Pcell evaluation for cmos14soi/nmos/layout has the following error(s):
*WARNING* (DB-270002): ("eval" 0 t nil ("*Error* eval: undefined function" dbSetShapeColor))
*WARNING* (DB-270003): Error kept in "errorDesc" property of the label "pcellEvalFailed" on layer/purpose "marker/error" in the submaster.
Great, so I know that the error is the dbSetShapeColor call. I've found that in the kit using grep:
neko:/kits/cmos14soi/relIBM/cdslib$ grep -r dbSetShapeColor *
Binary file cmos14soi/cmos14soi121.att matches
Binary file cmos14soi/x_single_shape/layout/layout.oa matches
Binary file cmos14soi/cmos14soi610.att matches
Binary file cmos14soi/64bit/cmos14soi121.att matches
Binary file cmos14soi/64bit/cmos14soi610.att matches

So, I now know that my missing function call resides in those .att files. Is there anyway for me to check which/if those .att files are "loaded"? 

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how to use ADE_L to plot waveform after command line simulation

June 21, 2014, 12:07 am
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 hi,everyone

        I am simulating a big circuit .When I  use ADE  simulating it,it would take a long time to initialisation,and then begin to simulate.But when I use comnand line to simulate ,for example use command "spectre input.scs" ,it starts  quickly.After it finished,I can use wavescan to plot waveform,but it is not convenient as in ADE using results--direct plot.

       My cadence version is IC615 MMSIM13.0

        Could anyone tell me  how to use ADE_L to plot waveform after command line simulation?

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Evaluating Error vector magnitude function

June 22, 2014, 1:00 am
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Dear all,

 

           I am simulating a 16- PSK modulation scheme. I am generating the different phases of the carrier using delay elements. I need to see the effect of delay mismtach on the EVM. May I know how this can be done? Please note that I am using a square wave as a carrier rather than a sinusoid. 

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Regarding more DRCs at routing for 28nm designs using routeDesign command using encan advanced license

June 22, 2014, 4:55 am
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Hi,

Iam working on 28nm design using soc encounter with the following steps,

Placement -> prectsopt -> CTS -> postcts_opt for setup and hold -. routing -> postroute opt

1)Iam using padding for the flops at placement stage.

2) CTS done by using the CellHalo for clock buffers,

3) Routing is done using routeDesign command

Here, at routing stage Iam getting lot of DRCs around #6000 while routing the design, but when I do verifyGeometry with the default options Iam getting around 1000 DRCs. confusion with this number. 

"routeDesign shows different DRC count than VerifyGeometry" 

Iam using the following nanorouting settings for routing the design. 

 setNanoRouteMode -routeWithViaOnlyForStandardCellPin 1:2

setNanoRouteMode -routeWithViaInPin false
setNanoRouteMode -routeUseMultiCutViaEffort medium
 setNanoRouteMode -drouteAutoStop false
routeDesign
 
Please give me suggestions/advises inorder to reduce the number of DRC count at routeDesign.
Is any switch should be added while routing the design with setNanoRoueMode?
FYI Iam using EDI 11.13V tool. 
 
Thank you,
 
Waiting for response. 
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Functional Coverage Question

June 22, 2014, 8:19 am
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 I have 2 coverpoints.

 Each coverpoint has auto generated bins as well as user-defined bins.  In pseudo-code, I will describe them as follows:

 cp1: 

     auto_bins,

     userdefined_bin0, userdefined_bin1 ;  

 

cp2:

     auto_bins,

     userdefined_bin2, userdefined_bin3 ;  

 

Now, I want to cross cp1 and cp2.  But, in that cross-coverage, I am only interested in crossing the userdefined bins and not the auto_bins. 

cp1_x_cp2:

cross cp1, cp2 {

    userdefined_bin0 intersects with userdefined_bins_2, 3 ;

    userdefined_bin1 intersects with userdefined_bins_2, 3 ;

    **************** This is being achieved but the auto bins are also coming into play.

     *************** How do I ignore the auto bins??

}

Thanks,

 ashfaqh

 

 

 

 

 

 

 

 

 

 

 

 

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human ordering sorting challenge for skill

June 19, 2014, 2:29 am
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Hi 

I've numerous times come across the issue of sorting strings in a more "human way of thinking fashion" 

I've played around with the different sorting predicates like 'lessp, 'alphaNumCmp, 'axlStrcmpAlpNum but none are really sorting in the way I would need. I had hoped the 'axlStrcmpAlpNum would do what I wanted, but mixed strings are a challenge.

Example (end sorting result that I would like)

"22" 

"111234" 

"111237"

"111a32"

"112323" 

"11235a" 

"11235f"

"abc211"

"xyz211"

I've come across some LISP code for this, but must admit that although I've done a lot of skill programming the code at the link below are a bit "black magic like" for me, it does not translate directly into a skill program

http://rottcodd.wordpress.com/2007/12/15/human-order-sorting/  

So maybe someone could shed som light on how to transform this into something usefull in Skill.

Hint:  http://www.davekoelle.com/alphanum.html has a number of other language implementations for the same type of sorting, it actually explain and illustrate the problem very nicely.

Thank you very much in advance

Best regards

Ole 

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Orcad Capture: Changing a homogenous symbol into a heterogene and add a part - Can it be done?

June 22, 2014, 11:47 pm
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Dear forum, Is there a way to change a homogenous part to a heterogenous and add a part within it? What I would like to do is to edit say a 4 part gate, delete the (hidden) power pins, add a fifth "power part" and place the power pins (visible) on that part. There are large libraries included with the products, but having the power pins hidden is IMHO not a safe way to control the power routing, especially since I want to reuse symbols for logic families with different supply voltages. 

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Cadence distributed processing with SKILL

June 23, 2014, 3:09 am
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Hello,

I have a skill code that i wish to run in distributed mode. The distributed processing user guide eloborates the setup of distributed mode option with OCEAN commands. does the same setup apply for skill code?. If not, is there any other option which could speed up the code runtime?.

Thanks in advance

Best Regards

Taher 

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Unable to get expected output

June 17, 2014, 11:52 pm
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i am unable to get expected output for forward converter circuit of attached doc, becoz of transformer modeling(2 primaries and 1secodary) can anyone help me to model the transfomer.

I tried to create model from pspice modelling app available in latest release but iam not getting output,thank you in advance. 

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Free Viewer

June 23, 2014, 8:18 am
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 Our company firewall blocks *.exe files and I cannot download the latest viewer file because of this.  Is it available in a zip format somewhere else?  

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