Conflicting values netlist error
Hi all,I got below netlist error after swap pins enable for part(Heterogeneous).. please help me.. #105 ERROR(ORCAP-36004): Conflicting values of part name found on different sections of...
View ArticleCustom Vias
Greetings,I've been on this forum under various names depending upon employment status and I need the forum's help once again. I have a package called PowerBlades. The end mounting to the PCB have two...
View ArticleFree Physical Viewer 16.2 - Find Comp functionality
I recently upgraded my free physical viewer from 16.0 to 16.2, and have found that when I use the 'Find By Name' functionality, a successful hit on a component no longer causes the viewer to zoom in...
View ArticlePAD_DEF output in 16.6 ISR22
I have just installed IRS 22 for 16.6 and now have problems with the Valor ODB++ output, there is a new field in the standard output which seems to stop this working. PAD_STACK_CATEGORY. Does anybody...
View ArticleHelp to create a time varying resistance in PSpice
Hello all, I am Shilpa and i wish to simulate a circuit where in a time varying resistance is required.The idea is to vary the resistance over time which will give a varying voltage output across...
View ArticleOA to CDB convertion script
HI, we are presently using cadence 5.4.1 vertionwe need OA to CDB convertion ,how we will convert, is there any script to convert that please tell me that code thanks,venkatasiva
View ArticleProblems visualizing results with Wavescan - MMSIM 6.2 - IC 5.1.14
Hi, I am using MMSIM 6.2 with IC.5.1.14. I have to run a large tran simulation with spectre and I've been having problems at the moment of visualizing the results with wavescan. According to...
View Articlesoc 8.1 installation
when trying to install sco encounter 8.1 using install scape. it shows the release Base_SOC08.10.000_lnx86 but after that clicking on the NEXT button takes to the window where the installation products...
View ArticleRegarding simulation of VARACTORS using MOS and finding quality factor
hi using IC 5.10.40 I am working on VCO using MOS Varactor(B D S connected and inversion mode)but i am facing the problems listed here..1 Finding the capacitance and quality factor. I also want to plot...
View ArticleSKILL++ class slots
I have a few question on slots in a class. Given the following class that implements string utilities:defclass( String() ()((str @initarg nil) ; The string(len @initarg nil); The length of the string...
View Articlewhat kind of VIAs does people use?
Hi,I am new about PCB design. I personaly would like define all kind of via, all kind of combination(as you see in picture 1) I also saw a tutorial shows that only define b/b via between each layer.(as...
View ArticleXL pin issue
I have a block that was copied from an existing cell and when I try to add new pins with the "generate selected from source" button I get the error (Bus net base name in name 'DAC2' matches a scalar...
View Articleinitial statement issue in IFV
Dear Sir/Lady:I have a question while using IFV, there is a simulation model in my design, after running the verification flow for several cycles, I did not find PRINET was set to 1b'1, this seems to...
View ArticleCadence IC5.1.41 libInit.il
Hi,I wanted to know is it possible to overwrite the libInit.il file, which is specified in the project area by a local version of the same??I am actually trying to load a user defined set of...
View ArticlePower as input for behavioural source in a transient Spectre simulation
Hi there.During a transient simulation in Spectre, I would like convert the device power to a voltage signal. I tried using a behavioural source as follows:E1 (1 0) bsource v="M1:pwr"Unfortunately,...
View ArticleHow to zoom to a particular location in layout editor(IC5141) by giving...
Dear All,I want to ZOOM IN to a particular location by giving (x,y) co-ordinate in virtuso layout editor.Could any body please tell how it can be achieved,Kind Regards,
View Articlenot able to create via in clone
Hi I am trying to create via inside clone using the command dbCreateVia(cell_id obj_id obj_origin obj_orient v_params) Inside clone, but it is creating in the cellview not inside the clone.
View ArticleAccessing C code generated from veriloga compile
Is it possible to access the C code generated by the veriloga compiler?With the ahdlcom option on I get "ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. ..." problems. The log files tell me...
View ArticleDoes OrCAD Capture and PSpice 16.6 run on windows 8.1
I am searching for a new laptop to buy. I found one but it runs on a windows 8.1 OS. So, I wanted to ask if OrCAD capture and PSpice will run on windows 8.1 or not.
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