Transistors in series
Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place. My question is: when I change the multiplicity or the number of finger in a FET transistor, it...
View ArticleWhich simulator is best to use for Mixed-Signal Simulation?
For example I can have some HDL design compiled and implemented in Encounter Digital Implementation, then I can have that design imported in Virtuoso Encironment as a layout or higher level schematics...
View ArticleInstalling IC615
I am having trouble installing IC615 on ubuntu 13.10 (64 bit). When i try to run iscape.sh i get the following errorException in thread "main" java.lang.UnsatisfiedLinkError:...
View Article"FreqSelect" function under the Orcad
hello, can you tell me where I can find the "FreqSelect" function under the Orcad software? thank you
View ArticleRe: Help for SUB 1Volt BGR(band gap reference)cadence simulation error
Respected mam,kindly help by consedering this cadence Simulation error i'm getting version Virtuoso 6.1.5What possible changes i can make for resolving the erronious simulation Please reply at my...
View ArticleLVS error for MOS parameters
Hello all, I got error message in LVS in parameters mismatch tool(Virtuoso XL), the message is : Err: Sch MOS missing params: l,w ; Lay MOS W/L/NF 5e-06 1.8e-07 12 I don't have any idea about...
View ArticleReuse Module with different stackup
Hi,I am new to the reuse design concept.Is it possible to use the 4 layer stackup reuse module(*.mdd) in 8 layer stackup or 10 layer stackup board without chaning the reuse module stackup?Thank you
View ArticleQRC: extract only down to a certain layout level
Hi everybdoy,is it possible to extract the parasitics of a layout only for some parts of the hierarchy?E.g. I would like to extract the parasitics of the "top level" and the level below to see the...
View ArticleFeature Suggestion: Design space reference angle
It would be useful to be able to rotate the global design space angle, allowing sub-groups of components to be routed while placed on an odd PCB.For example: a group of components are rotated at 30...
View Articlehow to netlist parameter value for different simulator
Hello, I would like to netlist a device D1 with a parameter named P1 with two values A or B (theses values are straings).In the CDF of the device I defined a string parameter P1 with two values A or...
View Articlelength matching
Hi all..i am new to pcb design...i dont have knowledge in length matching the nets..length matching should be done between clock signal and data signal...can u pls tell me the procedure for length...
View ArticleAllegro 16.6 snap to cline
For some reason when I am routing Allegro will not snap to a cline. Vias and pins work but it refuses to snap to a cline.
View Articleconformal -Lec
I am verifying a RTL vs NEtlist created by synopsys DC compiler. Some modules are black boxes by the tool. I think they are some memory modules. What is the way to preserve the interface information of...
View ArticleIGBT literature reference in the reference manual
Hi,In the IGBT section of the reference manual the following literature reference is given:[1] G.T. Oziemkiewicz, “Implementation and Development of the NIST IGBT Model in a SPICE-based Commercial...
View Article"FreqSelect" function under the Orcad
hello, can you tell me where I can find the "FreqSelect" function under the Orcad software? thank you
View ArticleNetlist to Schematic size problems on IC5141 (Width and Length are 0)
Hello.I'm trying to generate a Schematic from a Netlist file on IC5141. Although I can successfully import the Netlist file and actually generate the Schematic, there is a problem with the devices'...
View ArticleA question about the pad size?
Have a question about the pad size? I am new about Cadence design. And now, I am making a footprint for a part. The pdf file shows you the min/average/max of each pin. when you make a footprint, which...
View ArticleHow to insert file containing Design Variables in Analog Design Enviroiment
Hi,I'm attending a stage in STMicroelettronics. I have to realize a digital filter IIR, for thr firts simulation I can't use any HDL. Then, I have to realize a filter using a LUT, when I'm using the...
View Articleexternal_driver_input_slew VS set_input_transition
Arent those two commands doing almost the same thing for RC compiler?
View ArticleError on creating wire in Virtuoso
Hi, When i'm trying to create a wire in Schematic editor of cadence Virtuoso i'm getting the following error and wire is not getting created. I'm able to copy/move/extent the already existing wires...
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