Problem highlighting part
We recently did our first design using Allegro version 16.5 and I am having problems highlighting parts when using the viewer of the same version. In the past I could zoom in anywhere on the PCB,...
View ArticleViewing a shell ascii file and creating a shell path
I am using the view() function to open an ascii file from the shell, but it opens the file in the form/window in Virtuoso looking at the tail end of the file. EG if the ascii file is larger than the...
View Articlegetting the label at tree view
Hi everyone,I am currently working on an interface where treelist is used. the form will display list of layers present in the design in tree list. every item is set to be displayed with a check box.....
View ArticleHow to clear DRC or LVS highlights in Layout editor window ?
Hi,I m new to SKILL. Can anybody suggest me for how can i clear DRC or LVS highlights in layout editor window(in cadence virtuoso) using Skill programming.Regards,skulkarn
View ArticleError while trying to explore about get_inst_coverage
Hi, I'm trying to observe the difference between get_coverage & get_inst_coverage with the following example;class trans; rand logic wrd; rand logic [2:0] addr; rand logic [7:0] din; rand logic...
View ArticleBreaking down foot print libraries into categories
I find the one big footprint library very cumbersome. Has anyone broken theirs down into sub categories, ie; resistors, capacitors, ic's, etc..... If so are there any special constraints for the...
View ArticleVoids areas on plane that won't go away
In the attcahed picture I have some void areas in the gnd plane that I can not get rid of. I have tried turning all colors on to see if there was somthing hiding there, but nothing shows up. Screen...
View ArticleCross section of .brd for import to Ansys / Percentage of Copper per layer
Hello, I have been asked to provide a cross section / cutt-out of a .brd to send to Reliability Engineering for import into Ansys for Thermal Analysis. Is there a way to cutt away unwanted...
View ArticleConnecting symbol shapes to internal layer
On the connector shown below I want to connect the shapes around the perimeter to the internal gnd layer. I have selected each shape and assigned the net "gnd" to each but I get no ratsnest showing a...
View ArticleOrCad CIS on mySQL server
I am using OrCad CIS 16.5 and I would like to use my company server to host the CIS database. We are using mySQL. I have set up a database with the properties as described in the help and created a new...
View ArticleRunning DIVA extraction in batch mode for IC5.14
Hi, I am trying to extract parasitics of a layout. I am wondering how I can invoke DIVA extraction in shell? Thanks,Reza
View Articlenoise on bits of same bus
Hi All, Iam working on cross talk analysis of mixedsignal design . and the SI analysis will do noise on delay and glitch noise analysis. In my deisgn , the bits of bus are custuom routed and as per...
View ArticleIdentical circuits BUT completely different device behavior
Ok, so somehow magically (why the calculations and theory does not match with the pspice model is another post) a circuit begins to work in a project. So I copy this circuit over to a new project (to...
View ArticleEditing symbols
Greetings,A newbie here. I have used Orcad for a very little while, so a learning curve. I placed a transformer on the page, and want to remove the "pin numbers' from the symbol. How do I go about...
View ArticleConnect macro power to top level
Hi,I have read alot about this issue (in this forum), but still don't having some problems.i have power strips + power ring in my block, and i use lefOut -stipePin in my block to generate the lef file...
View ArticleTo add skill files to the taskbar
Hi all, How to add skill files in the menu bar?Please explain what steps to be followed? Rajan
View ArticleError on NC drill (by layer) output file
Hello,I am designing a 4 layer board with some blind/buried vias. So on “Manufacture -> NC -> NC Drill” I selected under “Drilling” the option“By layer”. There are then generated 3 output files...
View ArticleCannot add pins to a block....
I am encountering a problem adding pins to a block. Oddly this is only affecting the right hand side of the block (the output side). I can add pins (Add Pin>type the pin name> click on the block...
View Article4 layer design stackup
Anyone doing this with ground on layers 1 & 4 and signals on 2 & 3?Surface mount components on one side or both sides.Pro's and con's?
View ArticleTransistors in series
Hi! First of all, sorry if I'm posting it in the wrong place. Moderator please move it to the right place. My question is: when I change the multiplicity or the number of finger in a FET transistor, it...
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