How to get coordinates of layers
Greetings!I want to get coordinates of layers of the selected object.What what SKILL commands or program will I use?For example:I have a resistor in a layout, I select it then execute a SKILL commands...
View ArticleOrcad capture cis slow starting in windows7
I have a problem with Orcad CIS loading on windows7. When I try to start the program it takes several minutes (approx 10 minutes) before I even see the splash screen for Capture. After it loads...
View ArticleGerber Compare in Orcad PCB Designer
Hi all,Is there an equivalent to GerbTool in orcad layout which i can use in Orcad PCB Designer?I want to compare gerber changes between revisions.Thanks,Nigel
View Articlefinding usage/references/instances of a cell in same/other libraries Virtuoso...
Sorry to ask such elementary question but web search didn't turn up anything for us.We have a Virtososo schematic/layout full custom design now with many libraries. Is there some way to see if a...
View Articlewaveform processing question in Virtuoso ViVA
My system: Cadence IC615 Sometimes when I do a DC sweep, I need to rearrange the X and Y axis. For example, in a voltage DC sweep, I got two signals shown on the viva. Var1 vs voltage, and Var2 vs...
View ArticleaxlDBCreatePadStack Warnings...
Hi All, have any of you seen these errors before? I'm getting closer and closer to creating my padstacks,but still get some warnings that don't seem to point me in the right direction. (I'm a...
View Articlepreserving a subdesign from optimization
I wont to generate a fixed delay, for which I have used multiple NOT gates and instantiated in the top design. While synthesizing, RTL compiler optimizes the gates added and put a direct net without...
View Articlepassing IRUN command-line arguments into vsif file?
Hi,I use command-line arguments in my script and it looks like thisirun ... +define+MY_ARG ...I can run stand-alone simulation with different MY_ARG to different tests.How can I reuse my script in a...
View ArticleEXPEDITION SCH TO CONCEPT HDL SCH
Hi All, If possible to convert expedition sch into cadence concept hdl sch?Regards, Karthik.
View ArticleRe-using design constraints with different stackups.
Hello, Is there a way to re-use design constraints if the stack-ups are different? I just finished a 12 layer board and am now working on an 8 layer board which requires the same constraints?...
View ArticleConformal- LEC
Hi When I run Hirarchial compare using conformal, write hier_compare dofile dofile.do is not created. It is throwing the error like "could not find the starting comment hierarchial do file generated by...
View ArticleCustomize Datatips
Is there a way to customize what is displayed for datatips? On symbols, the default is the REF DES and the SYMBOL. I would also like to add the PACKAGE_HEIGHT_MAX so I do not need to show element and...
View ArticleRF Load Pull advice
I am attempting to design a circuit employing a low power transmitter IC. I'd like to couple it with an amplifier module, and in the process match it's output to an antenna. For this, I'm considering...
View ArticleCustom DC Operating Point Definitions or Overwriting the .dcOpInfo.info file?
Our foundry provides a subcircuit model which produces correct ID-VD and ID-VG curves. However, the .OP vdssat (based on BSIM definition) is wildy different than what is expected, ~200mV higher.What I...
View ArticleSkill++ - create another class that is composed of two instances from another...
I've created a class that is supposed to represent a two-dimensional point. It is defined here: defclass( gf_2dPoint () ;superclass ( (x @initarg x @reader getX @writer...
View ArticleLVS verification for gds file from Cadence SOC Encounter
Hi,How to verify the LVS for gds file from Cadence SE. I have used 65nm STM standard cells for generating netlist file for layout and schematic design. i am getting mismatch erros in Calibre LVS...
View Articlehelp with board outline gerber
Hi everyone, I'm having a great deal of difficulty completing/verifying what should be an easy task - I would like to generate a .art (gerber) file that describes the board outline. In this case, I...
View ArticleOrcad capture cis slow starting in windows7
I have a problem with Orcad CIS loading on windows7. When I try to start the program it takes several minutes (approx 10 minutes) before I even see the splash screen for Capture. After it loads...
View ArticleInteractive verilogA models in Spectre
Dear all,I have questions related to the Verilog-A models in Spectre,- can I create three voltage-controlled current sources using Verilog-A and use it in the same schematic page since two of them are...
View ArticleaxlDBCreatePadStack Warnings...
Hi All, have any of you seen these errors before? I'm getting closer and closer to creating my padstacks,but still get some warnings that don't seem to point me in the right direction. (I'm a...
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