How to change signal globewise in concept hdl?
I was using VCC3V3 in some page and some page I was using VCC3V3_FPGA so I want to change all signal to VCC3V3_FPGA in one shot in Allegro Design Entry HDL. Regards,Giri
View ArticleISFET layout design
Hello,Is it possible to design an ISFET sensor thru Cadence Design Enviroment tools? If it is possible, I guess it may be necessary to breach some design rules, isn't it?Could anyone guide me thru this...
View ArticleHow can I simulate 'PLL Noise PSD' ?
I'm fresh designer for PLL. I want to simulate 'PLL Noise PSD' on transient simulation.I had used Analog design environment -> results -> direct plot -> main form.but I couldn't see funtion of...
View ArticleLayer not showing in layer palette
hi, So a new layer was put into the tech file. I've looked at the tech file it appears to have been added correctly. Layer is: NSD with a purpose of polygate. Problem it doesn't show up in the...
View ArticleHow to use BSIM-CMG models to build and simulate FinFET circuits
Hi All,I need to simulate FinFET based circuits I have BSIM-CMG codes and models from http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG_LR this includes veriloga files.va and files.include and...
View Articleencounter streamout by preserving the partition
Hello All,I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted...
View ArticleOffset voltage measurement
I am desiging a low noise, low offset opamp using chopper stabilization and ripple reduction loop. I need to know how to measure the offset voltage. Is it related to montecarlo simulation ?pls guide me.
View ArticleGaN Gate Drivers
I'm looking for any material (books/papers) regarding high speed gate driver ICs and the operation of GaN power transistors that includes theory and practical examples. I have found a few documents...
View ArticleWhat is the name of the schematic create menu
I know the edit menu called schEditMenu.I tried schCreateMenu but it is not correct.Where can I found the names for all the menus? Thanks in advance.Eyal G.
View ArticleHow can I transfer a integer variable from verilog to VHDL?
Hi Candence: How can I transfer a integer variable from verilog to VHDL?As the code shows bellow:tb_top is verilog module;vhdl_top and bellows are vhdl module. module tb_top; integer...
View ArticledbGet query inst/term driver
I have a list of max transition terminal violations from a third party tool : ( .ie. <inst>/<term> max_tran tran violationcoding/CODING_SW_REGS_inst/v8_lite_inst/A 0.6800 0.7106...
View ArticleLink for "Virtuoso Spectre Circuit Simulator User Guide"
Dear All,I am looking for the latest "Virtuoso Spectre Circuit Simulator User Guide".While searching in cadence online support it gives me many links with "Virtuoso Spectre Circuit Simulator User...
View ArticleChange parameters in pcDefinePCell code body
Hi, I have a normal pcell that you can give certain parameters. I want to check in this pcell if certain parameters are between a min and max value, and the reset the parameter to this value. How is...
View ArticleRegarding Smoothness in transient analysis
Dear All,I created a verilogA module.What it basically does is as below:-It is a simple sine wave generator. I stored the sine wave time & amplitude in a text file for one period of the sine...
View ArticleSetup materials with materials.dat
Hi, I want to create some own materials so that they are available for selection @ "Material" column of "xsection".i modified the default materials.dat (Just copied a few lines of an existing material...
View Articlemixed-signal AMS simulation error
Hi, I was trying to do a simple mixed-signal simulation with AMS in Cadence ADE environment (6.15). In the setup there are two inverters. One inverter A has schematic view and the other inverter B...
View ArticleRemoving 0 width warning during artwork generation
I always used to use 0 width text for footprint silkscreen, and then when they used in project I just select specific width for all undefined width lines. But since I upgraded Allegro 16.6 to S015...
View Articlegvim or nedit SKILL syntax highlight in Linux
Hi, I am new to Linux and looking for some customization of the text editors in Linux.I am wondering how I can customize the text editors in Linux (such as gvim or nedit) to highlight the SKILL...
View Articleplease help on verilog and vhdl combination problems
Hi Candence,I met a problem in using verilog and vhdl:1) I use verilog to make a testbench while the DUT all are made by VHDL2) I want to initialize the lower level memories in DUT. I have tried to use...
View ArticleCreate application form trigger??
Hello, We want to create our custom button on on a certain predefined by some of our third party vendors Application form. It can easily be done with code like bellow: hiAddField(certainForm...
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