ADEXL: backannotation of transient operating points for montecarlo points
Hi all! Could anybody please tell me how can I backannotate transient operating points in ADEXL for single montecarlo points? I am able to do it in "Single Run, Sweeps and Corners" mode, but when I...
View Articlecross on Power and Ground pins
Hi, a cross "X" is found on each ground and power pin when i create BGA or flip chip using text-in method.is there a way to make the cross invisible?Â
View ArticleSimulating Frequency Multiplier Phase Noise in PSS/QPSS/PNOISE/QPNOISE
I am trying to simulate a frequency multiplier. For the purposes of this discussion, use the case of a 100MHz source multiplied up to 500MHz. This is a 5X frequency multiplication. The multiplication...
View Articlesave option not working for ac within transient
I'm running a transient sim and using the actimes option to run ac analysis at various points.   tran_ac tran stop=150u errpreset=moderate write="spectre.ic" method=trapgear2 \...
View Articlegvim or nedit SKILL syntax highlight in Linux
Hi, I am new to Linux and looking for some customization of the text editors in Linux.I am wondering how I can customize the text editors in Linux (such as gvim or nedit) to highlight the SKILL...
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Does u0 and vth0 viewed in simulation result reflect default constant value...
After any Spectre simulation, does U0 in model parameter field mean the low-field mobility of the very original one or the one infulenced by STI/WPE or any other issues? Simply put, ,This image gives...
View Articlehow to save the current display layers using SKILL??
Hi..How can I save the current display layers I have in my layout by using SKILLcommand?? I looked at the SKILL vocabulary, I cant find any command that would apply to this case?? Here is the steps I...
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ADE(Analog Design Environment) display problems
Hello,I am using Virtuoso IC6.14 and MMSIM 7.1 or 10.1 version for simulation.But I found the result of the simulation was upside down(Please check the picture).I am currently using CentOS 6.4 for the...
View ArticleMissing components in bom and pcb editor 16.5 place manually option
Hi, Im using cadence 16.5 version tool. i used many no of resistors in my schematic, when i generating a BOM, there is no one component in resistor name which i was using. i created netlist also and...
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OP Amp not simulating properly
Hi, I recently completed a basic opamp circuit in order to properly simulate a full wave bridge rectifier circuit.However, I encounted som problems with the output that was directly linked to the opamp...
View ArticleHow to copy/version a design into the same ConceptHDL project library?
ConceptHDL allows you to save multiple designs in the same library for a single project. However, I can't figure out how to completely copy a design (retaining all sch, sym, etc views) to a different...
View ArticleExport Physical not adding pin numbers until component is replaced in ConceptHDL
I recently ran into a strange issue where Export Physical (with back annotation enabled) was not adding pin numbers to the component symbol in ConceptHDL. However, if I deleted the symbol from the...
View ArticleDesign Lock in HDL / Read-only Design
Hi,I would like to ask how to make the schematic design a read-only file. All previously created schematic designs will be uploaded in the server. These designs can be used by other design engineers...
View ArticleLaunching SP analysis with GoldenGate from ADE
I did set up my GoldenGate environment, integrated it with Cadence and as a simulator instead of Spectre selected GoldenGate. I ran the simulation, I checked the output file, it all looked right, in...
View ArticleGeneric power symbols in design reuse blocks in ConceptHDL
What is the best way to create a design reuse block with generic/configurable power symbols? For example, I'd like to create the design reuse block with a generic power symbol "VDD_IN", and when the...
View ArticleTo find the empty area between the matched MOS
In several layout matching we  place the devices (nmos or pmos) in 1, 2 ,3,4,5 (rows)  etc and route through the empty space . so i would like to caluclate the empty area between the device through...
View Articlehow to measure power consumption of a circuit in cadence spectre
Hi,I would like to know how can I estimate the power consumption of a circuit say an inverter circuit in cadence environment. I searched through the internet, but couldn't find any suitable doc that is...
View ArticleDC - AC inverter circuit design in PSpice
 Hi everyone,I am looking for an inverter circuit design drawn in PSpice. I have done all possible searches online and all that is coming up is DC-DC converters or AC-DC rectifiers. I am new to PSpice,...
View ArticleWhat does Constant hierarchical Pin(s) means in RTL compiler?
Hi everybody,When I check the design in RTL compiler 10.1 after synthesis, I get the following summary for my design.I know that Assigns are not good and should be removed before importing the design...
View Article*E,TRFILEIO: file I/O Error using textio.all library in Sigasi
I'm trying to use the std.textio.all library but I'm getting the following error:  ncelab: *E,TRFILEIO: file I/O error.cannot open 'uart_rx_inputs.txt' for readingThe input file, uart_rx_inputs.txt, is...
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