Timing ECO steps
Hi,In my design (post route) i need to do some timing optimization eco. mainly upsize some cells.I will appriciate if you can write down the steps i need to do in order to do so.I am guessing its:...
View Articledisplay "program running process" on unix terminal or new window
Hi:I want to use skill to invoke "calibre " command and want to display the "running process" on unix terminal or new window like assura running process. I only find ipcWaitProess and ipcReadProcess,...
View ArticleHow to switch off STI's influence in a simulation just for methodology study?
Hi,In BSIM4.5 and later release, the SIT (shallow trench isolation) effects are considered. Is there anybody who knows how to control the STI in any simulation.Say, if I want to switch off the impact...
View ArticleGet default via spacing and enclosures
Hello,I use dbCreateVia() function to create vias with variable cut Rows and Columns determined by the width of the path connected to the via in the layout view. In order to compute the cut Rows and...
View ArticleKitchen Units And Doors
Kitchen Units And Doors Kitchen Units And Doors Try looking at www.kitchendesign1.co.uk.They have some amazing designs and prices.Kitchen Units And Doors
View ArticleUsing existing .brd for template.
I have a .brd file (Allegro 16.5) that I want to use as a template for a new board. I would like to remove all electrical components and netlist and leave behind mounting hole, etc. I would then like...
View ArticleHelp to add a menu item before a separator
I used to use a simple SKILL program that reads in the default allegro.men file from each base release, performs my company customizations, and then reads out the modified file. It worked pretty well...
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how to plate the edge drill
I have a small board, the outline of the edge have two half circles, it need copper pated wall. I know we can use via if it is in the middle of the board. But how about the edge ?The board outline is...
View ArticleDRC and LVS error
Hi allI have a .GDS2 file that got it from SOC Encounter and now i want to check DRC & LVS. To do this I import my .GDS2 file in cadence( CIW--> File--> Import) and after that i can see the...
View ArticleHi
Dear SirI Have Doubt it Pcb Layout I did't get Layout desgin Please help meI Have create NetList and Desgin Check Rules ,But not create layoutwat reasons....Please Refer meWithDevan
View ArticleTCL/TK utilities
HI ALLI have 16.3V Capture but there is no utility in Acessories like "TCL/TK utilities" any reason?RegardsNayyier
View ArticleHow to make a custom pad for a flex circuit
How can I make a custom pad for a flex circuit? It looks like I can use a "shape" (.ssm), but how do I do that? What I want is a circular pad with a "hold down" tab but have only a circular mask..
View ArticleAbout leYankFigs , How to yank more than 50 nLevels?
Hi All , I want to use this command , the layout design hierarchy depth more than 32 , it's 50 , If i set 50 in ;x_nLevels , it will show *WARNING* noname :Illegal hierarchical level of 50...
View ArticleSV Help ! how can dump the wave from class ?
Hi, all Now I define a class ,and initiate it to a new class varible, I want to dump some signals from it , how can I get that ?
View ArticleInclude a IP netlist during Synthesis of a complete design
I have an IP whose netlist is available. I want to include this netlist during Synthesis of my complete SoC. I do not want to modify anything inside this Netlist. What are the steps to be followed...
View Articlemissing fillet report
Hi all,is there skill for missing fillet report and no need to go quick reports?thank you
View ArticleHow to setup Cadence ADE to simulate basic digital blocks successfully
Hi, I am using Virtuoso IC6.1.5 with IBM BiCMOS8HP technology. It runs well in ADE for analog design. But when I imported digital library of this technology,draw a basic circuit schematic with AND...
View ArticleInverted text inserted into a shape
Is there a way to write a text inside a shape in a inverted way i.e. like doing voids corresponding to the text letters inside the shape ?
View ArticleOrCAD Capture Pinswapping Issues
I'm attempting to pinswap pins between parts of a multi-package heterogenous FPGA part. I can't get the back annotate function to work even though I believe I have set up the part properly to support...
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