encounter streamout by preserving the partition
Hello All,I started with a vhdl behavioral filter design, did structural synthesis using Cadence BuildGates, place and route with soc encounter, imported output of encounter to virtuoso and extracted...
View ArticleName on .ENDS does not match .SUBCKT
Why I am getting error message " Name on .ENDS does not match .SUBCKT" when I change parameters of an IC or transistor? Every subcircuitry has its ENDS.
View Articledifference between cell_rise and rise_transition in library
Hi All, I have a doubt regarding library ,In library for a combinational cell there are cell_rise and rise_transition 7x7 tables defined as below , cell_rise(delay_template_7x7) {------------- }...
View ArticleWhat's the difference between cellView~>prBoundary and cellView->shapes->lpp ?
when lpp=list("prBoundary" "boundary") ? I mean, what's the cellView~>prBoundary supposed to do?Thank you.
View ArticleAssigning Options in CIS Config file
Greetings everyone....I will most likely have several questions concerning the CIS Config file over the next week or so. I am looking to edit the CIS config file to set up the default directory as well...
View Articlea question about how to use config
say, if I have an instance named I2<1:0>, can i set different views for I2<1> and I2<0>?I am using IC615. Thanks!
View ArticleTransient flicker noise simulation
Hi, I want to run a transient simulation in Spectre with flicker noise ON. I set both Fmin and Fmax values. I am interested in the noise in the first 100ns of the simulation but I noticed that I have...
View Articlereseting instance labels
Hi all. Is there any way to reset all the labels (instance names) in a schematic view hierarchially? Thanks in advance.
View ArticleFailed to compile ahdlcmi module library
Hi, The icfb version is 5.1.0 06/24/2004 17:30, (only the base CDs), when I tried to simulate a circuit which module file contains ahdl_include "res_va.va" statement, it gets error saying that it can...
View ArticleResistance between pin and terminal
I'm trying to find out what the resistance is, from an extracted view, between a pin and the terminal of a transistor. Is there a way to do this with the Parasitics Tool? Using the Parasitics tool I...
View Articleencounter streamout by preserving the partition
After floorplanning my design in Encounter, I specified partition to few of my blocks in the design. I did gds streamout and imported the .gds file to virtuoso. The netlist extracted from virtuoso do...
View Articleresizing a schem symbol
Hi folks.Looking for some advice on how one goes about moving the pins to a rezied symbol. I basically made the rectangle smaller, but when i drag the pins into meet this, the still follow an...
View ArticleHow to import BOM To Capture
Hi friends, Anybody please explain me how to import the BOM to capture.
View Articledefine PFB footprint for multiple onbjects
Say i Have 10 headers on my page, and i want to define there footprint which is indetical for them all. Is there a quick way to do them all at once, (maybe an app) or do i have to click into each of...
View ArticleError when calling and evaluating skill function in ADE-L Parametric Analysis...
Dear all, I've got a problem to which I couldn't find answer.I've made a customized skill function to do calculation and evaluation after PSS analysis. It takes in time domain waves from PSS and...
View Articledxdesigner libraries to OrCAD libraries
hi,Is their any conversion facility available for dxdesigner libraries to capture libraries..? Using Cadence tools!!
View ArticleMissing .lib files?
Hello,I'm trying to simulate a fairly simple two-BJT amplifier, which uses MPSA18 transistors, which I found with the "transistor.olb" library. When I try to simulate, though, I get these:...
View ArticleKitchen Units Doors
Kitchen Units Doors Kitchen Units Doors Try looking at www.kitchendesign1.co.uk.They have some amazing designs and prices.Kitchen Units Doors Kitchen Units Doors
View ArticleMore descriptive DRC violation datatip for Ravel DRCs
By default, the tooltip that pops up when you hover the mouse pointer over a Ravel DRC violation in the design window does not show the Ravel violation description, but the for Ravel purposes rather...
View ArticleError evaluating ocean expresstion
Hi everybody,I got the following error when doing Monte Carlo analysis.Error evaluating ocean expresstion bw = bandwidth(VF("/VOUTP") 3 "low")It seems that the error is always there whether the...
View Article