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Printing/Saving to file Statistical Parameters from a MC
Hi all,trying to visualize statistical parameters from a large netlist, I got an error because the number of lines of output would be greater than 1900, so the window got truncated.However, I also got...
View Articlehow to add synthesizable delay in design
I am trying to add a delay of 3ns and 5 ns in my design but it not synthesizable in RC-compilor..anyone have idea how to add a synthesizable deslay in verilog........
View ArticleAsynchronous FIFO design
 Hi,     I am new to logic design and trying to design an Asynchronous FIFO. can somebody suggest some good docs to read? regards,abhinavpr
View ArticlePSpice: coax cable models
Hello,As far as I've checked, coax cable models in PSpice (TLine.lib library file, which could be open in any ASCII editor) have some definition which looks strange for me. At least, I don't understand...
View Articlefind current window when qrc "view command file" is display
Hi, Im doing the next skill code. when I try to save the txt file ( view window) that open I fail to do so. it seems that the current window is not the view-text window, no matter what Im trying:...
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Short between IO filler blockage and IO pad pin
Hi,In our design we have IO fillers with blockage for the IO ring power & ground stripes, and IO pads with pins for the same busses. When placing fillers between the IO cells, we see short...
View ArticleNetlist does not respect CDF Pinorder
I am trying to incorporate a synthesized digital block into my custom layouts. To complete LVS I have the netlist of the digital block in a cdl file and have made a CDF property with the order of my...
View ArticleChange Spectre directory
Hello,I have two question:First one:I want to change the directory where the ADE is locating the spectre. I tried to source the runSimulation file for a test circuit and the directory for spectre is...
View Article[Help] How to calculate the Cds?
Hi guys, In the OP printing list of a MOS transistor with a BSIM3v3 model, there are a lot of capacitances, such as cdd, cdg, cds, cdb. In order to calculate the total capacitance between drain and...
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cant start specctra with design
 Hello is any one knowingsolution for this please help me.When i click on route->PCb router->Route Automatic then its showing error as cant start specctra with design Thanks abubakar
View ArticleFree Tutorial Videos (OrCAD and Allegro)
Wouldn't it be great if there were a stack of 2 minute long videos, created by product experts, offering free point tutorials on all aspects of PCB and schematic design with Cadence PCB Editor (OrCAD...
View ArticleMake macro block pin visible in higher hierarchy
Hello all,I have the following situation in SOC Encounter:I have made a design X, which uses some standard cells, and some macro blocks. One type of macro block should have an input or output port....
View ArticleDRC errors: package to place keepout spacing
Who can tell me how to solve it ?Thank you very mach!
View ArticleDrill File Not Recognized
I'm having problems getting my board made. We have a small machine on campus capable of printing a board (I think only 1 sided), but the technician is telling me that the drill file generated by...
View ArticleHow to write text on a PCB that brings up copper etching
Hi everyone, I want to write text on a PCB so that when I make a gerber file and send it off for production, it will come back with text etched out of copper.I am using Cadence Allegrro PCB designer...
View ArticleGetting renamed ref des into Capture
I have sorted through and figured out how to rename the ref des on a board. How do I import this info into Capture now? It only creates a .log file, not a .swp file which Capture is looking for....
View ArticleHow to Add Specially Created Via Padstacks to Just the Design Database vs....
For a design, trying to keep some specially created via padstacks out of the general library path and instead just keep with the design database. In the Allegro Constraint Manager, there are two...
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View ArticleIncluding subcircuit netlist for hspiceD
Hi, I am attempting to include a netlist for a subcircuit, and I am using hspiceD as my simulator/netlister. I have tried a couple of methods, and nothing seems to quite get me all the way. (FYI, I am...
View ArticleTwo Layer Board with copper fill on top and bottom; Problems with Void...
Allegro 16.3. I have created a simple two layer board with copper fill on top and bottom. This copper fill is my ground plane. I followed a manual that explained how to create the shape, assign a net...
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