Meaning of "seed" usage in defining PDF in VerilogA.
Dear All,Could anybody tell what is the function of seed parameter in a PDF in VerilogA.Any way we are giving mean.sigma value then I wonder what exactly the integer 'seed' does ? Kind Regards,
View ArticleSymbol Etch ?
Hi all ? I want to get some parameters of a symbol as assembly, palcebound... and my symbol having a shape type "ETCH". I try to use sym->children and then I got all symbol's parameter except...
View ArticleMonte-Carlo simulation and writing to file from VerilogA
I'm running 100 MC simulations from ADEXL. My setup includes a verilogA block which among other things also writes results to a file. The problem I'm having is that in my case 10 MC runs use the same...
View Articleinput and output noise simulation with Spectre Noise analysis?
Hi, I would like to know if the output noise (V-rms) obtained when I simulate the output noise of a circuit with Spectre simulator (Noise) include the noise of ALL the components referred to the output...
View ArticleUpdating Part (Schematic Symbol) in Design Entry HDL
Hi,I'm using Project Manager - Design Entry HDL in creating schematic diagram. I placed a diode symbol in the schematic diagram. After awhile, the diode symbol was modified (Pack_Type was added in...
View ArticleDesign Lock in HDL / Read-only Design
Hi,I would like to ask how to make the schematic design a read-only file. All previously created schematic designs will be uploaded in the server. These designs can be used by other design engineers...
View Articlecloning group
Hi.How can I clone a group in layout? I can create instance and place them at several places in layout. When I modify one instance, all other identical instances will change at the same time.. But I...
View ArticleConstraint manager in 16.3
Hi all,I am using Allegro 16.3 ,I am doing DDR 2 routing with 2 Memory devices .I am unable to understand COnstraint manager for routing od Address/Control using Tpoints and how to use SigXploer for...
View ArticleHow to let a attached library's techLibName becomes itself library name?
Dear All, I create a library A ,compile a new tech fileI create a library B , attach to library A , Now i want to let library B to has its own techfle , so i copy the tech.db from library A(In IC...
View Articleverifyconnectivity
After doing the verify connectivity, I am getting the error "dangling wires" . Please guide me how to solve the problem
View ArticleIs there a way to use CTS with differential (diffpair) clocks?
Hi, I am researching an implementation idea to use Clock Tree Synthesis (CTS) to route a clock tree that consists of a differential clock. The desired results would be a clock tree that is routed as a...
View ArticleODB vs Gerber Layer naming conventions and Drill Figure matching
I have been sending board houses and Contract Manufactures both Gerber and ODB++ files, since not all of them can read ODB++. I am now in the process of making Artwork Layers, X-section and ODB match....
View Articlehow to add coverlayer and stiffener for FPC
hi , I am new to fpc, don't know how to add coverlayer and stiffener for FPC, i am looking for help ,thanks! using allegro 16.3
View ArticleNoise simulation in Cadence
Hi, I'm learning Noise Simulation in Cadence. The circuit is just a simple common source amplifier with a noise-less resistor as the load. What I want to do is to observe the noise situation for the...
View Articlesweep variable "bs" in hb, then use VAR("bs") in output expression, not plot...
Hi, Maybe I found a bug recently. (Cadence IC 615, mmsim 12.11 )Firstly, I sweep variable "bs" in hb, then use VAR("bs") in output expression, it can not plot when run in ADEXL, but it can plot...
View ArticleSpectreRF installed?
I am wondering if SpectreRF is installed with our IC615.06.15.511 and MMSIM11.10.445 installation. In the simulator option of ADE I only see hspiceD, Spectre, UltraSim, ams, SpectreVerilog and...
View ArticleCreating .lib file for a flipflop
Hi everyone, I'm using ELC to characterize my design library in UMC 130 nm technology. All of my cells except the flipflops have been characterized and I'm getting errors that some of the Hspice...
View ArticleChange the grid size while routing in Allegro with a hotkey, Keep routing at...
When routing a design more often than not I change the grid when routing.I created a hotkey to do this and indeed the grid does change but when the hotkey executes I loose the cline segment I had...
View ArticleHow to get a layer selected a PIN?
Hi expert, I want to know a way to get a layer where I select any pin in.If a pin is through type and I select the pin at internal layer named Layer2, I want to get ths Layer2.and If I select the pin...
View ArticleverifyGeometry violations, Encounter 11
I'm having a strange issue with verifyGeometry in Encounter 11. After routing my design, my tcl script runs 'verifyGeometry' before saving the design (.enc) . 'verifyGeometry' reports that there are...
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