Problem in Running UltrasimVerilog
Hi,I have a circuit with all custom deisgned module, and a verilog functional module for generting the input stimulus for my custom designed block. When I try to simulate using UltrasimVerilog as my...
View ArticleRefdes Attribute ?
Hi !I want to get some atrtibute of refdes, such as rotation, xy, textBlock , isMirrored ( ex: refdes-> rotation), but i don't find any function to do that. there is only Text Attribute. How can...
View ArticleProblem in Running UltrasimVerilog
Hi,I have a circuit with all custom deisgned module, and a verilog functional module for generting the input stimulus for my custom designed block. When I try to simulate using UltrasimVerilog as my...
View ArticleFillets in Allegro PCB Design L
Hello,Can any one tell me how to put the Fillet, teardrop in Allegro PCB Design L (legacy).I saw some tutorial but under Gloss i can not see any options for the fillets.How to do it????? thank you,
View ArticleHow to change component class (OrCAD Signal Explorer)
HiI'd like to change component class in PCB Editor (16.2) with OrCAD Signal Explorer before extracting xnets. The only way I could do it was to change the refdes and use setup advisor->device...
View ArticlePCB Ascii file
Hi,We are into manufacturing of PCB's and for one of the PCBs manufactured we want to perform flying probe test and for this we need a PCB ascii input file for the Seica FPT.We have a .brd file for the...
View ArticleAbout the viewing of the information of the nodal voltage between schematic...
Hi, everyoneWhat I used: Cadence IC51.41.151 /// Spectre 10.1.1.412.isr23 After running the Spectre to extract the nodal voltage, Can we print this informationto the Layout XL(Layout Editor) on the...
View ArticleReading a parametrized cdf parameter
Hi, I am trying to read the CDF parameters of a FET.My problem is that some of them refer to other CDF parameters via iPar().So if I do:...
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Check Parallel lines if intersect
given image above,I would like to check both segments (maroon/orange line could be in any slope value) which are parallel to each other if they intersect.dashed lines are the perpendicular lines of...
View ArticleMIL-STD-1553 trace routing
A lot of boards I have done over the years have used MIL-STD-1553 communications. Normally these were boards where the coupling transformers were located close to the connector. The manufacturer of the...
View ArticleModify film_reorder.il
I have been looking at the program "film_reorder.il" (available at cadence.com) and have found it useful but would like to make a small modification to it. After you have selected a layer to be moved...
View Articleumc180nm symmetric inductor
iam using cadence with umc 180nm foundary file,where can i find the symmetric inductor in your tool.how to get quality factor for symmetric inductor
View Articlehow to reduce explored
Hi, Iam using IFV for formal property checking and i have some of the assertions/Property explored.How to make them either pass/fail. ThanksBharath
View ArticleAMS Designer & Parameter Arrays
Hello everybody,I would like to run a mixed mode simulation using some VerilogAMS code. In this code I currently use some parameter arrays to hand over parameters. Unfortunately I get the message that...
View ArticleASCII waveform file format for Virtuoso Visualization and Analysis XL?
I have some waveforms captured from a high speed scope that I'd like to display alongside spectre simulation results in "Virtuoso Visualization and Analysis XL" viewer using ADE-XL. I'd assumed it...
View Articleproblem: W and L of a transistor not shown in edit-> object-> properties
When editing a transistor in schematic editor L (version 615), the width (w) and length (l) are not shown in the form so that they can not be changed. The CDF parameters shown are M gates per device,...
View ArticlePower Stripe - Power Via Generation in Encounter
I am trying to use a power ring, special routing, and power stripes for my power routing. I can set up the ring, special routing, and stripes correctly as far as location is concerned. However, I am...
View ArticleHow often does AMS flush outputs by default during a simulation?
Iam running a long transient simulation using AMS designer. I would like to flush the simulation results periodically in order to view results as the simulation progresses. Do we have flushpoints and...
View ArticleERROR (VACOMP-1008): Cannot compile ahdlcmi module library when I practice...
I got this error when I was practicing Cadence AMS Methodology kit (05B_AnalogBlockDesignOptimization) using IC6.1.5. My OS is Unix 32-bit."ERROR (ADEXL-5011): While simulating run LocalOpt.1, point...
View ArticleSanity Check how do I Compare netlist from capture and Allegro.
In other PCB/SCH tools I have used it was possible to generate a netlist from both the schematic and then from the completed board so as to verify the actual board did indeed match the...
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