Pspice ( Spice ) simulation from virtuoso.
I will like to capture a schematic in virtuoso and run pscice simulation on it.but i am runing into a netlisting problem
View ArticleCDB to OA Conversion: Layout Issue
Hi,Cadence version: IC6.1.5Lately, we have been converting our design database from IC5 to IC6, using cdb2oa script, that was shipped along with IC6.We managed to convert the database without any...
View ArticleClik here to view.
Irregular Pad
Hello, I am currently new on using Cadence 16.6 and new in this forum. I need some advice on making an irregular pad. I'm currently making a foot print for a current sensor. (please see image below)...
View ArticleSet Max line width as nominal in the constraint manager.
Good afternoon, Is there a way to set the maximum line width in the constraint manager as the "nominal"? I have a power trace with a min of 10 and max of 50. 95% of the trace will be 50. The...
View ArticleERROR [NET0011] Netlist failed or may be unusable.
Trying to make a PCB from a layout file.I create a netlist and get the following errorI attached a screen shot of the connector but im not sure it will do any good.what does the error meanive gone...
View ArticleChanging the artwork output dir
I want to write artworks to a design dependent output directory.I have a script to create artworks, olddir = "output"outdir = "output/123456-ND-A"axlSetVariable("ads_sdart" outdir) ; set working...
View Articlemodifying layout made with from capture netlist
I havent done a lot of work with layout and any type of projects linked to capture.im having a very difficult time trying to make a simple modifcation to a layout made from a capture circuit in that...
View ArticleSymbols & Padstacks
Hello, I have a general question here. Say I am given a Symbol (.dra & .psm) to use in my design. I do not have the padstack used within this symbol (.pad). Am I still able to open the .dra...
View ArticleADE L: could not open logFiles during a parametric sweep on a transient...
Hi cadence ADE L suers, My cadence is installed on Redhat linux and I am running Virtuoso 615.When I do a parametric test (sweep temperature) on a transient simulation, the simulation stopped after the...
View ArticleForcing via connections
I have a multi-layer design with multiple ground plane layers. But these have issues with ground loops. How can I set something in PCB Editor 16.5 that will only connect vias to one ground plane layer...
View Articleencrypter skill
Hii want to write a skill to encrypt my skill file but my code doenst wok.. please help..here is my code: (defun encrypt () file = axlDMFileBrowse(nil nil ?optFilters "Skill files(*.il)|*.csf|Dat...
View ArticleClik here to view.
analog_extracted simulation
hi,first: sorry for my bad english! i want to simulate my design by using the "analog_extracted"-layout. in the "environment options"-window i wrote "analog_extracted" at the beginning of the "switch...
View ArticleOrCAD library icon and links
I am looking at an OrCAD library, discrete.olb in this case, and noticed that some of the symbol icons (which look like a little NOR gates) have a little line in them. I think they are somehow linked...
View Articlerectifier impedance-simulation
hi,first: sorry for my bad english! i want to design the analog part of an RFID. to build an appropriate antenna i have to simulate the impedance at the hf1/hf2 pins of the analog part, especially the...
View ArticleAllegro Viewer will not start after upgrade
I just upgraded from allegro_free_viewer_16-5 to allegro_free_viewer_16-6. Right after the upgrade it worked fine but today I keep getting the message This application has failed to start because...
View ArticleShielded Twisted Pairs Cable Model
Hello,I am trying to simulate a Shielded Twisted Pairs cable.Can anyone tell me what is the best model to use on Pspice ?The cable has the following characteristics:Conductor Resistance: 37,5...
View ArticleHow do I delete clock groups (created via set_clock_groups)
Hi,I have been using set_false_paths between clocks, and found out that it is better to use clock groups using set_clock_groups. Therefore, I updated my SDC files, but I now have a slight issue. I use...
View ArticleHow do I change the "Drawing Origin Size" in Allegro 16x
I find the drawing origin size just a bit too small, was wondering is there a method to change its size so it stands out, i.e make it biggerThanks Scott
View ArticleSchematic file not paste in OrCAD 9.2 ???
Hi.. I had drawn schematic in OrCAD 16.0, in that i had copied the content of that schematic and try to paste it in OrCAD 9.2.But when i tried to paste it the capture 9.2 was closed...
View Articlemap copied placement to schematic components orcad pcb editor 16.6
I'm doing layout of a filter on diff paths..so the components (R, C & L) must also be placed symmetrically. I've done placement on one path and (for symmetry) copied the components & placed...
View Article