?How to display timing slacks for all path going through a specific cell...
I am looking for a way to visualize the timing slack for all paths going through a specific cell. The intent is to understand why the cell is placed close/far from a specific launch/capture flop ? Any...
View ArticleOrcad CIS LIte Opamps library -need help
Hi,I was using Orcad capture Cis Lite to design a small circuit, the circuit contain an opamp ELH0041G (Elantec). I could not see this component in orcad library. I even downloaded Elantec opamps...
View ArticleSetting Drill Tolerance in Drill Legend
All,While editing a .dlt file, I also wanted to set tolerance in the drill legend. What is the proper syntax to enter tolerance? Right now, all my drill tolerances come out as shown in the attached...
View ArticleEncounterDB Class Diagram (TCL objects, not Scheme)
Hi Folks,I was wondering where I could find a Class Diagram that describe the internal structure of Encounter's Classes (Digital Implementation Database).I mean, a netPtr is a a Class derived from...
View ArticleChanging the simulation temp from a task
I would like to change the simulation voltage/temperature in an AMS sim from a task general setup below I want the simulation to go through a bunch of states,reach a steady state,start a task that...
View ArticleAdding a permenent manu to a virtouso application window
Hello,I wrote a small script that add's a pulldown manu to my application window, in order to use it i open my cellview and run load("..script path..") in the CIW.I wanted to ask if there is any way to...
View ArticleRatsnest minimization length
HiI am anew user oforcadpcbandwould like to knowifit is possible tominimizethe length of theratsnestduringthe placementof a component andnot after it isplaced.Thanks
View ArticleError with Vendor-contributed Models in Simulation
I wanted to use AD8002 opamp in my design so I used the Vendor-contributed Models libraries from the downloads page here http://www.cadence.com/products/orcad/pages/downloads.aspx in the design to get...
View Articlecreate an NPN transistor in orcad 16.3
how to createan NPNtransistorwith personalparametersinorcad16.3?thank you
View ArticleDRC T error
I have a DRC error saying that T's allowed is set to pads and vias only. Where do I change this to allow T's anywhere?
View Articlebeginner question for monte carlo analysis in ADE XL 6.1.5.
Hi everyone, Previously I used PSPICE for my analog/mixed-signal simulations. Recently I tried to convert my design to Cadence Virtuoso-Spectre. I have been self-studying it for a few days. It is...
View ArticleUsing threads (cores) greater than 64 in APS
Dear All,Is it possible to use more than 64 threads in APS ? Kind Regards,
View ArticledeRegUserTriggers works only part of the time
Hi, im using deRegUserTriggers to run a skill procedure after a cell is openeddeRegUserTriggers("maskLayout" nil nil 'lg_PostInstallTrigger)my lg_PostInstallTrigger run properly if i open the cell with...
View ArticleFixed step size
Good day evryonecan you told me how to simulate with a fixed the step size ?in my simulation i use the MOSFET commutation and with maximum step size ORCAD variate the step size in commutation. But i...
View ArticlePhase noise of VCO
My name is Sharad, I am a student. I am designing a Voltage Controlled oscillator with current mirror in Virtuoso tool. I am unable to do the phase noise calculations. Please guide me with the steps to...
View Articlefind and replace multiple net expressions on a schematic
Hi there,I am trying to perform a "Find & Replace" of multiple netexpressions in Virtuoso SchematicI invoked Edit->Replace and in the drop down select box chose netexpr and in the text box typed...
View ArticleoptDesign command in SoC Encounter
Hi all,I was wondering if there is a way to disallow the movement of cells by the optDesign command in SoC Encounter.I have two power domains, where one power domain contains cells that are power gated...
View ArticleExtracted simulation ERROR (SFE-23): "input.scs" 17: c1 is an instance of an...
Hi,I am working on IC614 with the techonology IBM7RF. After extracting models from layout by Assura QRC, I tried to do the post-simulation with that extraction. However, a long list of errors (SFE-23)...
View ArticleVerilog simulation using verilog XL
Hi,i want to simulate a sample MUX21 realised on my schematic. I think, before going on the verilog XL , i need to put a load capacitor (classical cap) at the output to be able to see my output signal...
View ArticleRunning AC analysis after certain time of transient analysis
Dear All,One can run DC simulation at a particular instant of transient analysis.However, is it possible for the same for AC analysis ?In other words, I actulally want as follows:-I want to run...
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