Design Entry HDL - Console command to move to next page
Is there a console/script command to move to the next page? I would like to be able to perform operations on the entire design as opposed to just one page at a time. Thanks.
View Articlecomparing schematic netlists
Good day all, I have a thru-hole board in Orcad Layout. I have completed a smt conversion of the board in Orcad PCB Editor. While updating the schematic I spread it across multiple sheets since we...
View ArticleCTS and timing analysis for generated clock
I have a clock scenario as shown below. I have defined the B, A as clocks and X as generated clock. In my design X is 300KHz and A is 200 MHz and B is 50 MHz. Sel 2 will switch on the fly during the...
View ArticleMove traces with part
Let's say I want to move a resistor that is already routed by 0.015" to the right. I select placement edit and move the part, but the traces do not stay connected. What option do I need to select to...
View ArticleAutorouting
I normally don't autoroute anything, but I'd like to try it on a board I'm working on. Problem is this board is 8 layers and my seat is limited to 6 layers. I'm thinking I can remove the layers where I...
View ArticleAllegro DFA
Hello all,I would like to hear about users that are successfully using allegro DFA and have integrated their contract manufactures rule set into this process and how the integration was accomplished....
View ArticleHow to bring a dxDesigner netlist into PCB Editor
Hi All,i have created a new board in PCB Editor (v 16.3) and cannot see how to load in my netlist (please note i have never done any PCB layout before), can somone please tell me how to do this? My...
View ArticleAssigning net name to schematic symbol terminals
Hi,Is it possible to assign net name to the symbol term in the schematic through skill without creating wire(wire stub) from the terminal?Thanks,Eduard Raines
View ArticleciCacheFind with dbOpenCellViewByType
Hi,We are trying to asses how many layout cells in our current design library have constraints.I am trying to write a skill code to open every layout cell in my design library and check if it has...
View ArticleHow do I get ADEXL to update and fill in missing MonteCarlo trials that...
About 5% of my trials failed to converge. I don't want to run the whole lot again once I found a fix for convergence, so how do I do it?I did test the worst failing trial and get it to converge using...
View ArticlerodCreateRect taking too long
Using the profiler and also just putting print statements in I found that I am having trouble with rodCreateRect taking longer and longer to process. I have some very simple code:for(i 0 Nx for(j 0...
View ArticleRE: How to bring a telesis netlist into PCB Editor
It is required to have devices files for each type of component in your design in order to load a 3rd Party netlist. Most schematic packages that can generate a Telesis netlist can also generate the...
View ArticleInformation on dc_pivot_check option
Hi all, I'm simulating a circuit and get the following notice from Spectre: Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of...
View ArticlePhase noise to phase jitter for square waves
Hi,I'm simulating a free running oscillator for jitter and I have the following question:I have to run a "PNOISE - sources" simulation in order to recieve phase noise, since I have to filter the phase...
View ArticleCadence 16.6 GUI uses incorrect fonts so can't adjust certain tool parameters
Downloaded and installed Cadence 16.6. But when I need to adjust some parameters e.g. Create Netlist, adjust PSpice simulation profile, etc the fonts are too big hence not all the options fit in the...
View ArticleERROR in EDI 11.1 Import design
Dear Friends,i have a problem in enounter11.1 RTL to GDS ii tool, now i apply the input files in the IMPORT DESIGN tab netlist.v file and all.lef and power and ground nets vdd and vss. select top level...
View ArticleAMS Simulator support for SystemVerilog Math Functions
Hi, I was wondering if it is possible to enable support for the math functions in SystemVerilog (such as $sin) in the AMS simulator. When I try to run a systemverilog file including $sin built-in...
View ArticleIntegration of bsource in schematic views
Hi All,while looking into some models of my design kit I stumbled upon this "bsource" component.I then tried to instantiate one in a schematic, without success : I could not find any primitive with...
View ArticleHow to use hierarchy objects in dbLayerSize() command.
Hi all, I have to generate M1 layer under M2 in layout. cv=geGetEditCellView() figList2= dbGetOverlaps(cv list(car(pts) car(pts)) list("M2" "drawing") 32 t) dbLayerSize(cv list("M1" "drawing")...
View Articlefinding port side
Hi AllIs there any command or procedure to check the side of a given block port.I have a port i need to find on which side this port is placed (left or top or right or bottom).
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