Design Entry HDL Training
Hi there!Is there any training offering for Design Entry HDL here in Philippines?Please let me know. Thanks.
View ArticleGenerate External DRC
Hey,I saw a post recently regarding the skill command on generating external DRC, "axlDBCreateExternalDRC"... where could I get this? Thanks!
View ArticleOrCAD install killed Oracle VirtualBox
Installed Orcad demo and now Oracle VirtualBox is redirected to C:\SPB_data instead of c:\users\owner.VirtualBox.This killed my virtual machine firmware development environment. C:\SPB_data directory...
View ArticleEditing a wire with Virtuoso Schematic
Hi,I know it seems to be simple, but I can't change the name of wires in my schematic. I've tried to select the wire or the value of the name name and edit, but each time I've tried to change it, the...
View ArticleConformal-LP : Understanding liberty files.
Hi Conformal can read liberty files but the relevant lowpower special cellsare not recognised until those are specially specified with define_* cpf command.Since Conformal has all the information of...
View Articlehow to pass CDF parameter's value of an instance in schematic pcell to CDF...
An explanation of the problem I am facing is in order -I have created a schematic pcell (A) in which I am instantiating the instance of a foundry delivered pcell (B). There are some independent (e.g....
View ArticleHow to open a schematic window from a layout window
Hi All, Im looking to write code to open a corresponding schematic view from a layout window. I have the command below, (which uses predefined variables BSlibname1, BSblockname1 and BSviewname1 to...
View ArticleHow to Create Custom holes in PCB Board design
Hi, I have been developing a simple PCB board which contains a PIR sensor, an LDR and some other discrete components along with MSP430G2231. I have done outlines for my board according to its...
View ArticleDifferences between pins from digital and analog views of a schematic
Hi,I have a mixed schematic, mostly analog but with some embedded digital controllers. The digital parts were made in SystemVerilog and imported into the correct views in virtuoso together with the...
View ArticleQuestion about "Enable Antipads as Route Keepouts (ARK)"
Hello, I have defined an Anti Pad for the differential pairs of a high speed connector within the padstack for those pins. I have checked the box beside "Enable Antipads as Route Keepouts (ARK)" on...
View ArticleHandling rc/encounter generated pins in virtuoso
Hi,I have been working with a digital block made in SystemVerilog and instantiated into a larger analog design. The HDL was imported into the corresponding cell views in virtuoso and symbols were...
View ArticleMultiple SRAMs 1 data bus
I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple...
View ArticleDiff between 2 schematic revisions
Does orcad have a feature to show the differences between 2 schematic revisions?
View ArticleDrill Hole in a SMD Pad
Hi guys, kind of a general question this time. I have a farily dense board with lots of decoupling caps "0603" footprint. I was wondering has anyone used drill in a pad to get to the internal power...
View ArticleBlock level lib and lef
Hi All , Can you please suggest me in generating the block level lib and block level lef which are required at the top level. I mean what are the commands to generate these files.
View ArticleleSearchHierarchy() layers origin problem
Hi all, 1) I have used m1=leSearchHierarchy( cv cv~>bBox 32 "any shape" list(list("layer" "==" list("M1" "drawing")))) to get all M1 layers (from hirerchy also). But when I enter dbLayerSize(cv...
View ArticleAllegro Hangs with new hardware
We recently got new hardware and Allegro (16.3) will hang on occasion with the hew nardware. Has anybody else experienced this.New Hardware is Dell Precision T5500 running XP with Nvidia Quadro 2000...
View ArticleNeed a code for align instances by checking layer spacing
Hi all, I need a code which will align group of instances by comparing their spacing between specified layer ( like leHiAlign() in 615). Please suggest me about this. Thank you,Sarvani
View ArticleHow to learn Hierarchical design ??
Hi every one ,in my design Powersupply,Buffer,FPGA section and Reset circuit is there i need to do in Hierachical design i don't know how to start the hierarchical design .what is the use of...
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