CTS error
Hi, Im gettin the following during my cts. Can anyone explain what the error and how to get over it? Im using 8.1 Encounter. Any help is greatly appreciated.. Tracing Clock abc/OSOUT ... ** Pin...
View ArticleStreamOutTemplate files of IC615 and IC5141 are same or not?
Hi all, I am tring to run streamout for whole library in IC615 using a code( abWriteLibGDS.il) which is works well in IC5141 version. But i am unable to exicute streamout in IC615(i have used...
View ArticleKeepouts
I have a connector symbol that has two mounting holes. I want to have an area around the mounting holes where there can be no other components. On the bottom side there shall be no traces, but traces...
View ArticleHow to get a pop-up in foreground (when LibMgr refreshes)
Hello, I'm adding some menus in the library manager to get an SVN plug-in (based on some scripts from Poojan Wagh) and everything's going fine apart for the display of the pop-up forms. They appear...
View ArticleSKILL Variable
I am new to Cadence SKILL. I am trying to understand a SKILL script file containing many procedures. Many of these procedures use a variable which holds a constant list. But it doesn't seem to be...
View ArticleRatsnest color defaulting when dehighlighting
This drove me crazy for a bit until I found out what was happening.I set my ratsnest colors for a few specific nets to colors I wanted. Every now and then I would notice they had changed back to the...
View Article"Enhancement" requests
Who do I direct some feedback to for future "enhancements" to PCB Editor? I looked over the ton of fixes / enhancements for the 16.6 update and they must come from somewhere.Do I contact Cadence or go...
View Articlehow to refresh the .brd file in OrCAD PCB Editor?
Hi..Can any provide the solution to refresh the ratsnet in editor.Me had tried many times to find the command. But I can't found that.When i enter the refresh command that time the ratsnet connection...
View ArticleQRC menu does not load
I posted similar question in an old existing thread, I am not sure probably I should have post it in a new thread dedicated just to this.We have EXT10, the qrc version is: 10.1.1-p095The assura is 4.1,...
View ArticleFunctional Coverage with irun command
Hi, I trying to generate functional coverage using irun command.I have given "-coverage functional" in the elab phase. I am not getting any of the data orirnted coverage. Can anybody knows what I am...
View ArticleKeeping Library colors in Library Manager
Hi,I noticed IC6.1's new feature to allow you to "ASSIGN libname DISPLAY colorname". It works, but you have to hand-hack the cds.lib. But I'm coding some library utilities which utilize the ccp...
View ArticleOrCAD PCB Editor 16.6 Error
I was just curious if anybody has run into this yet. I installed the 16.6 upgrade last week, and it seemed to work just fine. This morning, when I tried to double-click a board (.brd) file to make...
View ArticleHow to handle pre defined generated clocks in .libs.
Hi, In the .libs, generated clock statements help defining the internal clocks being used in the entire design. When the .lib is design, internal clocks are reported or defined with the hierarchy of...
View ArticleHow could I do PSS and Pnoise analysis by the AMS simulator in ADE?
Dear all:I want to plot the phase noise of my closed-loop PLL where there were digital blocks in verilog and analog blocks in transistor level. I used AMS as the simulator, but I colud not find the PSS...
View ArticleBack Compatibility
Hi all,I have the project file which is simulated in pspice 16.2(in Windows XP), but when i open the project file in pspice 16.3 version(in windows vista and windows 7 both are home premium), project...
View ArticleHave to add all Libraries each time.
I generally add all the available Library all the time so it is easy search parts amoung them. When I was using OrCAD Capture Version 16.0, when I once add all the libraries, Capture use to remember...
View ArticleIs there a way to set Dimensioning Parameters using SKILL
Hi,Is there a way to setup the Dimensioning Parameters using SKILL?Thanks. Regards,Vijay Anandh Vela, CID
View ArticleEDI -> Empty Modules
Hello, First run through EDI 12.00 and I'm having a few teething problems.Successfully synthesised the RTL to verilog netlist but when I import the design I'm getting the following warnings (all...
View ArticleHow to use BSIM-CMG models to build and simulate FinFET circuits
Hi All,I need to simulate FinFET based circuits I have BSIM-CMG codes and models from http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG_LR this includes veriloga files.va and files.include and...
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