fanout problem in allegro pcb editor
Hello, i am facing problem without fan out feature of auto router with pcb editor.Images of before fanout and after fanout are attached. please advise.Adeel
View ArticleReference designators inconsistent in xprt and xnet files
Can any one help me to resolve the following error when i transfer netlist from capture to allegro using Allegro netlist Tab. " Loading... D:\OUT/pstchip.datLoading... D:\OUT/pstchip.datLoading......
View ArticleHow to lock the cell placement
Hi, can someone help in locking the placement of the Instance (should not be able to move the instance once i lock the position) in the virtuoso layout editor using skill..It is equvivalent to this...
View ArticleFunctionality of Cadence OrCAD 16.6 Lite version
I'm using Cadence OrCAD 16.6 Lite version. I'm able to design a circuit using MOSFETs and simulate it.Does this version provides the advance functions such as layout designing, PCB routing, etc. ?How...
View ArticleERROR(ORCAP-1245)
I'm running OrCAD Capture CIS Lite v16.6 and am trying to create a new project. I name my project, select Analog or Mixed A\D, and choose a newly created directory location. After I click OK, I get...
View ArticleA question about BB via
Hello, I have a question about BB VIA. I have a 6 layers board, which needs BB VIA.If I connect from top layer to third layer, should I use a layer 1 to layer 2 bb via then layer 2 to layer 3 bb Via,...
View ArticlePCB Artwork Directory??
When using Allegro PCB, how can I specify the path for the generated artwork? Currently it just dumps the artwork files in the Design directory, whereas I would like the artwork to go to a sub folder...
View ArticleQRC extraction failure with Calibre input
Hi AllWhen I run qrc_cmd file (content is listed at bottom), error was found and stop in pax step:WARNING (LBMISC-215001): file 'via1' is not a flat edge fileERROR (LBMISC-215002): it is a hierarchical...
View Articlesymbol library text resize skill code
Hi All, I was wondering if there is a skill script that will allow me to re-size the text of a symbol. Each time I have to do this, I need to go to setup->Design parameter-> text tab and select...
View ArticlePspice measurement results
Hello,I have generate a bode plot. I want to get the gain value which is fallen to -1dB based on the gain value at 1kHz. I know I could take the cursors, but I want to take the measurement results.For...
View ArticleMining information from RTL Compiler log file.
Hi All ! My first time posting on this forum. :)I have created a perl script that extracts the Path information that RC prints in the log file as it is working, and summarizes it. I have been finding...
View ArticleTransfering Title Block Attributes / Properties to Crystal Report
Hi Everyone. Thanks in advance to anyone that helps. I have been using Capture for over 10 years and I have come accross this problem before. This time I am reaching out for help. I have 'custon'...
View ArticleIBIS models simulator
Hi everyone, I am not sure if my post is in the right place. Anyhow I just downloaded Xilinx and Altera IBIS models. The Altera model is just a word file while Xilinx is a file with an extension .ibs ....
View ArticleHow to put data into memory for paste using SKILL
Hi All, I have a procedure() that can get a variable. Is there any methods can add to this block to put this variable into memory? which I could use mouse middle button to paste this data after I...
View ArticleInput Reffered noise in VGA (Variable Gain Amplifier)
Hi,I have to calculate "Input Referred noise" of variable gain amplifier. I choosed analysis--> noise --> freq. range, output noise [voltage] +ve and -ve node.input noise [port] port...
View ArticleSimulink SpectreRF connection problems
Hi,I am playing with the SpectreRF Engine Simulink connector and face severe problems.First of all, it is unuseable slow!I created a simple RF passive mixer. If I simulate it in Spectre alone it is...
View ArticleA question about BB via
Hello, I have a question about BB VIA. I have a 6 layers board, which needs BB VIA.If I connect from top layer to third layer, should I use a layer 1 to layer 2 bb via then layer 2 to layer 3 bb Via,...
View ArticleA question about merge two PCB design in the same panel?
Hello,I am merging two PCB layout into the same panel. I did merge the schematic first, and then import one PCB layout into another design. This process takes a lot of time and energy. I am just...
View ArticleFunctionality of Cadence OrCAD 16.6 Lite version
I'm using Cadence OrCAD 16.6 Lite version. I'm able to design a circuit using MOSFETs and simulate it.Does this version provides the advance functions such as layout designing, PCB routing, etc. ?How...
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