Eagle to orCAD?
I have some Cadsoft Eagle 6x designs. Are there any tools that would hekp me convert schematics or board files?
View ArticleCreate a BOM for Symbols on the bottom side of the board only ?
How does one go about generating a list for symbols located on the bottom side of the board only.It is not jumping off the page to me in reports..Thanks Scott
View ArticleHow to Generate Board Information
Hi,I am going to prepare Manufacturing information of my board. I have generated Art & Drill files. However, I see extra information in some PCB layouts of other manufacturers. For exmple, they...
View ArticleAdd via option not working while routing
Hi,I'm doing routing my design right now.While routing the ADD VIA option is not at all working after attempting so many times. Pls help me anyone to get a solution for this. Shreeja
View ArticleHow to learn PCB layout?
Good Morning All,I'm currently work as OrCAD Schematic Capture and build Schematic Symbol at work. I don't know anything about the OrCAD/Allegro PCB layout and would like to learn how to do it. I have...
View ArticleFootprint creation manually the refdes will get updated automatically?
Hi. I had small doubt in the footprint creation, i had tried to create the SMD Resistor footprint (SMR0805).In that, what should be the Refdes text should be entered. (i.e)., i should give text as R*...
View ArticleManually Created foot print is get not placed in board?
Hi.. I had created the footprint with specifications with what ever in data-sheet provided. When i am try to place in manually or place all components or place with room outline, the components is not...
View ArticleCheap K I T C H E N S London
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View ArticleHow to find out which env file is being used?
Hey guys, I edited my scriptpath in the global ENV file (located in the CDSROOT/share/pcb/text/ directory) as well as the local ENV file (located in the CDSROOT/pcbenv/ directory) both to have a new...
View Articlehow many colors are used in hilighting net in schematic
Hi, In the display.drf file, y0-y9 are defined, but y9 never appears, only y0 to y8 show up in highligting. Anyone has idea? Thanks!
View ArticleAssura LVS error in cadence 6
Dear Team, I am trying to do LVS for UMC65nm but it is terminating with the error. Please find attached LOG and screenshot of configuration.Let me know where is error and how can i solve it....
View Articlestatic cmos design
Hi guys, I need help with static cmos designing. how to design a single custom static CMOS gate(only one gate delay) that implements the function (NOT (A OR B OR C) ANDD)) and draw a MOS transistor...
View ArticleMagnetic Tunneling Junction (MTJ)- HSpice file simulation in ADE -Cadecne...
Hi, I am working on modeling of STT-MTJ using Cadecne Virtuoso. I am trying to simulate model ' MTJT.inc ' ( Ref : - Jon Harm, Farbod Ebrahimi- Univertsity of Minnesota ) using Cadence Virtuoso...
View ArticleCell View" window display at the bottom">virtuoso "New->Cell View" window display at the bottom
Greetings all,I'm running Virtuoso IC6.1.5.500.17.I've face a problem that when i click "File --> New --> Cell View..." at Library Manager, the "New File" window always display at the bottom, I...
View ArticleAllegro Impedance Calculator problem
Hi,I am working on my board Stack-up to tune Single/Differential impedances of my board in Allegro PCB 16.6. I see that Dielectric Constant is 4.5 (FR-4) ! even for Conductor/Plane layers. I don't see...
View ArticleHow to export FPGA pins information to a file
Hi all,I have my schematic & PCB in OrCAD Capture & Allegro PCB. I am wondering if there is a way to export FPGA pin numbers with Net Names to use it in a UCF file.I appreciate useful...
View ArticleError eval : unbound variable -cv How to solve?
Error message in CDS.log :Loading pCellGen.cxt*WARNING* Invalid libId - nil*Error* eval : unbound variable - cvexit cbx_1_0.ilSKILL program below: pcDefinePCell(list(ddGetObj("chb") "cbx_1_0"...
View ArticleCline to Anti-Pad distance DRC
Hi experts,Is there a way to look for clines where the gap/distance between the edge of the cline to edge of the anti-pad is less than the width of the cline? (see attached pic)Then if found, place a...
View ArticleUsing Views rather than Tables in a MySQL Database
Is it possible to configure the CIS Database to use Views rather then Tables in a MySQL Database?We are exporting data from our PLM database into a MySQL database, however it's not possible to export...
View ArticleBack annotation of a read only schematic
I am trying to create a back annotation script that parses through an file and back annotates the schematic which is in Read only mode.I am using geCreateHilighSet and geAddHilighLabel to create...
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