I lose waived DRCs during refresh; need skill code
Hi everyone,When I update symbols I lose all of my waived DRCs during refresh, is there a skill script to retain DRCs during refresh. My goal is the to able to export waived DRCs, and once refresh is...
View ArticleStrange scaling with multithreading in APS simulations
Hi, I wonder if anybody has seen anything like we observe for some of our typical anslog APS simulations when experimenting with different multitreading options on different hosts. Usually, when the...
View ArticleQuestion regarding reflection API
Hi all,I am trying to to set some vr_ad_reg fields with the set_value() method.This method require that the value will be passed as rf_value_holder struct , however I didn't find any good...
View ArticleRun Virtuoso 64bit
I'm trying to run virtuoso 64bit, and I have experience some problems. The most common one is Error while loading shared libraries (libGLU.so.1) I tryed to get the software version but didn't have much...
View ArticleMMSIM, ADE no Convergence during simulation...
Hi all,we just setup a new installation of MMSIM 12.11, IC6.16 and a 28nm PDK. After installing these tools and configuring PDK with the given scripts we built a simple NAND2 schematic to test our...
View Articlelibrary pointer
Hi All,Running SPB16.6. My current lib path is:PSMPATH = . symbols .. ../symbols C:/Cadence/SPB_16.6/share/local/pcb/symbols...
View ArticleHow to change sym extents for axlDBCreateSymDefSkeleton
HiI'm using axlDBCreateSymDefSkeleton to generate some symbols from text files, the problem here is that I need to feed the symextents as a parameter.I'm not dumping the libraries, but still would like...
View Article.drl file generation reg.
when generating NC drill file 'm getting the bellow error. WARNING: Design precision is greater than that of the drill output file data.Data rounding errors are very possible.ERROR: The number of...
View ArticleUsing RTL compiler PLE with DEF flow
I would like to adapt DEF flow with RTL compiler PLE. Is there any user guide or manual I can reference with? And should I get a detailed DEF from backend or I can just take a rough DEF (only...
View Articleexternal delay
is externa dealy input is equel to settting setup time ?external_delay –clock [find / -clock clock1] –input 200 -name in_con \[find /des* -port ports_in/*] externa dealy output is equel to settting...
View Articleupdate "cutSpacing" of a via
Hi guys,Long time lurker, first time poster. I first want to thank Andrew, Lawrence and other regulars for contributing to this forum. I have a simple problem that I can't seem to figure out and I am...
View ArticleUndo/recall selection
Hi, I'm looking to auto store a selection set in layout to create the option of an undo/recall selection. It would involve storing the selection set automatically each time a set of objects are...
View ArticleCreate a Via with the same parameters as what "auto" option provided on the...
Hi there,I am very new to this community. I am trying to implement creating via automatically using skill code. Thanks for all the information that you provided. I was able to place the via wher I...
View Articlesimple RC circuit
Dear all,Can some one help me to understand why the voltage at time zero drops to a value less than 1 V?Please check the attached file.Thanks,
View ArticletechDisplays: Failed to set layer-purpose
Hello, While generated a new techFile, i got the following WARNING INFO (TECH-180024): Created techfile library "xxx" INFO (TECH-180006): Compiling class 'controls'....INFO (TECH-180006): Compiling...
View ArticleRouting over voids
Does Cadence have a function to help us indentify routing over voids and splits for high speed nets we care about? If yes, where can i find it?Thanks,Patrick
View ArticleHow to find some parameters of OTA
hello everyone,I want to find some parameters like gain, phase, bandwidth, gain bandwidth product, unity gain bandwidth, CMRR, PSRR, slew rate. how can i find?is test bench required for it?Thanks in...
View ArticleSelecting a lot of objects in Virtuoso Layout Editor, Cadence 5141.
Hello. I use Cadence 5141. In Virtuoso Layout Editor I want replace library of elements in layout drsign. Use command Search... and then option replace. In case number of elements, for example,...
View ArticlePCELL: Specifying instance name in design
Hi friends, I have created a pcell for a Mosfet using PCELL menu in virtuoso layout suite L. To specify the instance name in my design i have placed a label [@instanceName] at the middle of...
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