Hello every body!
I will greatly appreciate your help.
In order to test a serial DAC I need to input the DAC with serial bits ( any pattern like 01110001111), one bit at a clock cycle. So my text file (bit_sequence.txt) looks like this:
1
0
1
0
0
1
.
.
.
Basically, I want a VerilogA model that reads "bit_sequence.txt" and output one bit at a clock cycle to my DAC circuit. I tried the following code. It compiles with no error, but I can't see the above pattern in my simulation. Moreover, after running simulation, the bit_sequence.txt gets empty! :)
module fileReader_1output(out1, clk);
input clk;
output out1;
electrical out1, clk;
parameter real vtrans = 1.0;
parameter fileName = "~/bit_sequence.txt";
integer fileHandle;
integer decimal_output;
integer captured_data;
analog begin
@ (initial_step)
fileHandle = $fopen(fileName);
@ (final_step)
$fclose(fileHandle);
@ (cross (V(clk) - vtrans,+1)) begin
decimal_output = $fscanf(fileHandle,"%d", captured_data);
V(out1)<= decimal_output; //captured_data;
end
end
endmodule