I have set up the basic mixed-signal testbench. Just imported a verilog file with clock generator, created a symbol for it and added it in a simple testbench where it is driving schematics built inverter cell.
I arranged the ADE GXL simulator with ams option. I Set up the connect modules for 1.8V. Everything seems fine.
When I run the simulation it fails with this error:
I have no idea what on earth does that mean? What is error 127?
This error can be seen in ncelab.log and simulation.log files, everything else in those log files does not have error, same goes for netlister.log and ncvlog.log files, no errors.
What that could be and how to fix it?
I arranged the ADE GXL simulator with ams option. I Set up the connect modules for 1.8V. Everything seems fine.
When I run the simulation it fails with this error:
Elaborating the design hierarchy:
ERROR: terminated with error code 127
ncelab: *F,SPRSER: Spice/Spectre file parsing failed.
I have no idea what on earth does that mean? What is error 127?
This error can be seen in ncelab.log and simulation.log files, everything else in those log files does not have error, same goes for netlister.log and ncvlog.log files, no errors.
What that could be and how to fix it?