14 hours and I couldn't figure out where the problem really is.
Somehow I cannot go past convergence error for my DNL-INL test model (attached the verilog-a behavorial model file).
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 7.0.1.179.isr16 -- 15 Jan 2009
Copyright (C) 1989-2007 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021.
Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.
Simulating `input.scs' on eecad29.engr.sjsu.edu at 11:59:39 PM, Sat Apr 26, 2014 (process id: 9033).
Command line:
/apps/cadence/MMSIM0701179/tools.lnx86/spectre/bin/32bit/spectre \
input.scs +escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre2_22708_13 -format sst2 -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 9033
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /apps/cadence/MMSIM0701179/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Using new Spectre Parser.
Auto-loading AHDL component.
Finished loading AHDL component in 0 s (elapsed).
Installed AHDL simulation interface.
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ (775)
Compiling ahdlcmi module library.
Warning from spectre during circuit read-in.
WARNING (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
Could not open ahdlcmi module library input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so
input.ahdlSimDB/1675_st45_EE288Project_adc_8bit_ideal_veriloga_veriloga.va.adc_8bit_ideal.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so: cannot open shared object file: No such file or directory
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/ (775)
Opening directory input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ (775)
Compiling ahdlcmi module library.
Warning from spectre during circuit read-in.
WARNING (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/ for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
Could not open ahdlcmi module library input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so
input.ahdlSimDB/1675_st45_EE288Project_DNLpart_veriloga_veriloga.va.DNLpart.ahdlcmi/Linux2.6.43.8-1.fc15.x86_64+gcc/obj/optimize/5.0/libahdlcmi.so: cannot open shared object file: No such file or directory
Circuit inventory:
nodes 10
adc_8bit_ideal 1
DNLpart 1
vsource 2
Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre2_22708_13, ).
************************************************
Transient Analysis `tran': time = (0 s -> 10 ns)
************************************************
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
Trying `homotopy = gmin' for initial conditions.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
Trying `homotopy = source' for initial conditions.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
Trying `homotopy = dptran' for initial conditions.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
Trying `homotopy = ptran' for initial conditions.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (VLOGA-5060): "/home/sh/shah6834/st45/EE288Project/DNLpart/veriloga/veriloga.va" 31: I12: Array access out of bounds near line number 31. Correct the problem and try again.
Trying `homotopy = arclength' for initial conditions.
None of the instantiated devices support arclength homotopy. Skipping.
Error found by spectre during IC analysis, during transient analysis `tran'.
ERROR (SPECTRE-16080): No DC solution found (no convergence).
The values for those nodes that did not converge on the last Newton iteration are given below. The manner in which the convergence criteria were not satisfied is also given.
Failed test: | Value | > RelTol*Ref + AbsTol
The following set of suggestions might help you avoid convergence difficulties. Once you have a solution, write it to a nodeset file using the `write' parameter and read it back in on subsequent simulations using the `readns' parameter.
1. Evaluate and resolve any notice, warning, or error messages.
2. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings. Print the minimum and maximum parameter value using the `info' analysis. Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.
3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.
4. Enable diagnostic messages by setting option `diagnose=yes'.
5. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.
6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file and set as many nodes as possible.
7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.
8. If simulating a bipolar analog circuit, ensure the region parameter on all transistors and diodes is set correctly.
9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.
10. Increase the value of gmin (on options statement).
11. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to somewhere in the range of 0.1 to 0.5 using `pivrel' (on options statement).
12. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.
13. Divide the circuit into smaller pieces and simulate them individually, but ensure that the results will be close to what they would be if you had simulated the whole circuit. Use the results to generate nodesets for the whole circuit.
14. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run the transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when all of the signals in the circuit are not changing) and write the final point to a nodeset file. To make the transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach will fail or be very slow because the circuit contains an oscillator. Often times the oscillation can be eliminated for the sake of finding the dc solution by setting the minimum capacitance from each node to ground (`cmin') to a large value.
Analysis `tran' was terminated prematurely due to an error.
finalTimeOP: writing operating point information to rawfile.
Error found by spectre during DC analysis, during info `finalTimeOP'.
ERROR (SPECTRE-16041): Analysis was skipped due to inability to compute operating point.
Analysis `finalTimeOP' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
element: writing instance parameter values to rawfile.
outputParameter: writing output parameter values to rawfile.
designParamVals: writing netlist parameters to rawfile.
primitives: writing primitives to rawfile.
subckts: writing subcircuits to rawfile.